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Miquel Raynal1f1ae152018-08-16 17:30:07 +02001
Miquel Raynald0935362019-10-03 19:50:03 +02002menuconfig MTD_RAW_NAND
Miquel Raynal8115c452018-08-16 17:30:08 +02003 bool "Raw NAND Device Support"
Miquel Raynald0935362019-10-03 19:50:03 +02004if MTD_RAW_NAND
Miquel Raynal1f1ae152018-08-16 17:30:07 +02005
6config SYS_NAND_SELF_INIT
7 bool
8 help
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
11
Stefan Agnerbd186142018-12-06 14:57:09 +010012config SYS_NAND_DRIVER_ECC_LAYOUT
13 bool
14 help
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
17
Stefan Roese23b37f92019-08-22 12:28:04 +020018config SYS_NAND_USE_FLASH_BBT
19 bool "Enable BBT (Bad Block Table) support"
20 help
21 Enable the BBT (Bad Block Table) usage.
22
Miquel Raynal1f1ae152018-08-16 17:30:07 +020023config NAND_ATMEL
24 bool "Support Atmel NAND controller"
25 imply SYS_NAND_USE_FLASH_BBT
26 help
27 Enable this driver for NAND flash platforms using an Atmel NAND
28 controller.
29
Derald D. Woods7830fc52018-12-15 01:36:46 -060030if NAND_ATMEL
31
32config ATMEL_NAND_HWECC
33 bool "Atmel Hardware ECC"
Derald D. Woods7830fc52018-12-15 01:36:46 -060034
35config ATMEL_NAND_HW_PMECC
36 bool "Atmel Programmable Multibit ECC (PMECC)"
37 select ATMEL_NAND_HWECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060038 help
39 The Programmable Multibit ECC (PMECC) controller is a programmable
40 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
41
42config PMECC_CAP
43 int "PMECC Correctable ECC Bits"
44 depends on ATMEL_NAND_HW_PMECC
45 default 2
46 help
47 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
48
49config PMECC_SECTOR_SIZE
50 int "PMECC Sector Size"
51 depends on ATMEL_NAND_HW_PMECC
52 default 512
53 help
54 Sector size, in bytes, can be 512 or 1024.
55
56config SPL_GENERATE_ATMEL_PMECC_HEADER
57 bool "Atmel PMECC Header Generation"
58 select ATMEL_NAND_HWECC
59 select ATMEL_NAND_HW_PMECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060060 help
61 Generate Programmable Multibit ECC (PMECC) header for SPL image.
62
63endif
64
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +010065config NAND_BRCMNAND
66 bool "Support Broadcom NAND controller"
Miquel Raynala903be42019-10-03 19:50:04 +020067 depends on OF_CONTROL && DM && DM_MTD
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +010068 help
69 Enable the driver for NAND flash on platforms using a Broadcom NAND
70 controller.
71
Álvaro Fernández Rojasd9f9bfc2019-08-28 19:12:15 +020072config NAND_BRCMNAND_6368
73 bool "Support Broadcom NAND controller on bcm6368"
74 depends on NAND_BRCMNAND && ARCH_BMIPS
75 help
76 Enable support for broadcom nand driver on bcm6368.
77
Philippe Reynes74ead742020-01-07 20:14:13 +010078config NAND_BRCMNAND_68360
79 bool "Support Broadcom NAND controller on bcm68360"
80 depends on NAND_BRCMNAND && ARCH_BCM68360
81 help
82 Enable support for broadcom nand driver on bcm68360.
83
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +010084config NAND_BRCMNAND_6838
85 bool "Support Broadcom NAND controller on bcm6838"
86 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
87 help
88 Enable support for broadcom nand driver on bcm6838.
89
90config NAND_BRCMNAND_6858
91 bool "Support Broadcom NAND controller on bcm6858"
92 depends on NAND_BRCMNAND && ARCH_BCM6858
93 help
94 Enable support for broadcom nand driver on bcm6858.
95
96config NAND_BRCMNAND_63158
97 bool "Support Broadcom NAND controller on bcm63158"
98 depends on NAND_BRCMNAND && ARCH_BCM63158
99 help
100 Enable support for broadcom nand driver on bcm63158.
101
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200102config NAND_DAVINCI
103 bool "Support TI Davinci NAND controller"
104 help
105 Enable this driver for NAND flash controllers available in TI Davinci
106 and Keystone2 platforms
107
108config NAND_DENALI
109 bool
110 select SYS_NAND_SELF_INIT
111 imply CMD_NAND
112
113config NAND_DENALI_DT
114 bool "Support Denali NAND controller as a DT device"
115 select NAND_DENALI
Masahiro Yamada8fc53822020-01-30 22:07:59 +0900116 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200117 help
118 Enable the driver for NAND flash on platforms using a Denali NAND
119 controller as a DT device.
120
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200121config NAND_LPC32XX_SLC
122 bool "Support LPC32XX_SLC controller"
123 help
124 Enable the LPC32XX SLC NAND controller.
125
126config NAND_OMAP_GPMC
127 bool "Support OMAP GPMC NAND controller"
128 depends on ARCH_OMAP2PLUS
129 help
130 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
131 GPMC controller is used for parallel NAND flash devices, and can
132 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
133 and BCH16 ECC algorithms.
134
135config NAND_OMAP_GPMC_PREFETCH
136 bool "Enable GPMC Prefetch"
137 depends on NAND_OMAP_GPMC
138 default y
139 help
140 On OMAP platforms that use the GPMC controller
141 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
142 uses the prefetch mode to speed up read operations.
143
144config NAND_OMAP_ELM
145 bool "Enable ELM driver for OMAPxx and AMxx platforms."
146 depends on NAND_OMAP_GPMC && !OMAP34XX
147 help
148 ELM controller is used for ECC error detection (not ECC calculation)
149 of BCH4, BCH8 and BCH16 ECC algorithms.
150 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
151 thus such SoC platforms need to depend on software library for ECC error
152 detection. However ECC calculation on such plaforms would still be
153 done by GPMC controller.
154
155config NAND_VF610_NFC
156 bool "Support for Freescale NFC for VF610"
157 select SYS_NAND_SELF_INIT
Stefan Agnerbd186142018-12-06 14:57:09 +0100158 select SYS_NAND_DRIVER_ECC_LAYOUT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200159 imply CMD_NAND
160 help
161 Enables support for NAND Flash Controller on some Freescale
162 processors like the VF610, MCF54418 or Kinetis K70.
163 The driver supports a maximum 2k page size. The driver
164 currently does not support hardware ECC.
165
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100166if NAND_VF610_NFC
167
168config NAND_VF610_NFC_DT
169 bool "Support Vybrid's vf610 NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200170 depends on OF_CONTROL && DM_MTD
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100171 help
172 Enable the driver for Vybrid's vf610 NAND flash on platforms
173 using device tree.
174
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200175choice
176 prompt "Hardware ECC strength"
177 depends on NAND_VF610_NFC
178 default SYS_NAND_VF610_NFC_45_ECC_BYTES
179 help
180 Select the ECC strength used in the hardware BCH ECC block.
181
182config SYS_NAND_VF610_NFC_45_ECC_BYTES
183 bool "24-error correction (45 ECC bytes)"
184
185config SYS_NAND_VF610_NFC_60_ECC_BYTES
186 bool "32-error correction (60 ECC bytes)"
187
188endchoice
189
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100190endif
191
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200192config NAND_PXA3XX
193 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
194 select SYS_NAND_SELF_INIT
Shmuel Hazan759349e2020-10-29 08:52:18 +0200195 select DM_MTD
Shmuel Hazan58983222020-10-29 08:52:20 +0200196 select REGMAP
197 select SYSCON
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200198 imply CMD_NAND
199 help
200 This enables the driver for the NAND flash device found on
201 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
202
203config NAND_SUNXI
204 bool "Support for NAND on Allwinner SoCs"
205 default ARCH_SUNXI
206 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
207 select SYS_NAND_SELF_INIT
208 select SYS_NAND_U_BOOT_LOCATIONS
209 select SPL_NAND_SUPPORT
210 imply CMD_NAND
211 ---help---
212 Enable support for NAND. This option enables the standard and
213 SPL drivers.
214 The SPL driver only supports reading from the NAND using DMA
215 transfers.
216
217if NAND_SUNXI
218
219config NAND_SUNXI_SPL_ECC_STRENGTH
220 int "Allwinner NAND SPL ECC Strength"
221 default 64
222
223config NAND_SUNXI_SPL_ECC_SIZE
224 int "Allwinner NAND SPL ECC Step Size"
225 default 1024
226
227config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
228 int "Allwinner NAND SPL Usable Page Size"
229 default 1024
230
231endif
232
233config NAND_ARASAN
234 bool "Configure Arasan Nand"
235 select SYS_NAND_SELF_INIT
Michal Simekc5587832020-08-19 09:59:52 +0200236 depends on DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200237 imply CMD_NAND
238 help
239 This enables Nand driver support for Arasan nand flash
240 controller. This uses the hardware ECC for read and
241 write operations.
242
243config NAND_MXC
244 bool "MXC NAND support"
245 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
246 imply CMD_NAND
247 help
248 This enables the NAND driver for the NAND flash controller on the
249 i.MX27 / i.MX31 / i.MX5 rocessors.
250
251config NAND_MXS
252 bool "MXS NAND support"
Peng Fan128abf42020-05-04 22:09:00 +0800253 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200254 select SYS_NAND_SELF_INIT
255 imply CMD_NAND
256 select APBH_DMA
Peng Fan128abf42020-05-04 22:09:00 +0800257 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
258 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200259 help
260 This enables NAND driver for the NAND flash controller on the
261 MXS processors.
262
263if NAND_MXS
264
265config NAND_MXS_DT
266 bool "Support MXS NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200267 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200268 help
269 Enable the driver for MXS NAND flash on platforms using
270 device tree.
271
272config NAND_MXS_USE_MINIMUM_ECC
273 bool "Use minimum ECC strength supported by the controller"
274 default false
275
276endif
277
278config NAND_ZYNQ
279 bool "Support for Zynq Nand controller"
280 select SYS_NAND_SELF_INIT
Ashok Reddy Somabb8448a2019-12-27 04:47:12 -0700281 select DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200282 imply CMD_NAND
283 help
284 This enables Nand driver support for Nand flash controller
285 found on Zynq SoC.
286
287config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
288 bool "Enable use of 1st stage bootloader timing for NAND"
289 depends on NAND_ZYNQ
290 help
291 This flag prevent U-boot reconfigure NAND flash controller and reuse
292 the NAND timing from 1st stage bootloader.
293
Suneel Garapati9de7d2b2020-08-26 14:37:22 +0200294config NAND_OCTEONTX
295 bool "Support for OcteonTX NAND controller"
296 select SYS_NAND_SELF_INIT
297 imply CMD_NAND
298 help
299 This enables Nand flash controller hardware found on the OcteonTX
300 processors.
301
302config NAND_OCTEONTX_HW_ECC
303 bool "Support Hardware ECC for OcteonTX NAND controller"
304 depends on NAND_OCTEONTX
305 default y
306 help
307 This enables Hardware BCH engine found on the OcteonTX processors to
308 support ECC for NAND flash controller.
309
Christophe Kerelloda141682019-04-05 11:41:50 +0200310config NAND_STM32_FMC2
311 bool "Support for NAND controller on STM32MP SoCs"
312 depends on ARCH_STM32MP
313 select SYS_NAND_SELF_INIT
314 imply CMD_NAND
315 help
316 Enables support for NAND Flash chips on SoCs containing the FMC2
317 NAND controller. This controller is found on STM32MP SoCs.
318 The controller supports a maximum 8k page size and supports
319 a maximum 8-bit correction error per sector of 512 bytes.
320
Kate Liu41ccd2e2020-12-11 13:46:12 -0800321config CORTINA_NAND
322 bool "Support for NAND controller on Cortina-Access SoCs"
323 depends on CORTINA_PLATFORM
324 select SYS_NAND_SELF_INIT
325 select DM_MTD
326 imply CMD_NAND
327 help
328 Enables support for NAND Flash chips on Coartina-Access SoCs platform
329 This controller is found on Presidio/Venus SoCs.
330 The controller supports a maximum 8k page size and supports
331 a maximum 40-bit error correction per sector of 1024 bytes.
332
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800333config ROCKCHIP_NAND
334 bool "Support for NAND controller on Rockchip SoCs"
335 depends on ARCH_ROCKCHIP
336 select SYS_NAND_SELF_INIT
337 select DM_MTD
338 imply CMD_NAND
339 help
340 Enables support for NAND Flash chips on Rockchip SoCs platform.
341 This controller is found on Rockchip SoCs.
342 There are four different versions of NAND FLASH Controllers,
343 including:
344 NFC v600: RK2928, RK3066, RK3188
345 NFC v622: RK3036, RK3128
346 NFC v800: RK3308, RV1108
347 NFC v900: PX30, RK3326
348
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200349comment "Generic NAND options"
350
351config SYS_NAND_BLOCK_SIZE
352 hex "NAND chip eraseblock size"
353 depends on ARCH_SUNXI
354 help
355 Number of data bytes in one eraseblock for the NAND chip on the
356 board. This is the multiple of NAND_PAGE_SIZE and the number of
357 pages.
358
359config SYS_NAND_PAGE_SIZE
360 hex "NAND chip page size"
361 depends on ARCH_SUNXI
362 help
363 Number of data bytes in one page for the NAND chip on the
364 board, not including the OOB area.
365
366config SYS_NAND_OOBSIZE
367 hex "NAND chip OOB size"
368 depends on ARCH_SUNXI
369 help
370 Number of bytes in the Out-Of-Band area for the NAND chip on
371 the board.
372
373# Enhance depends when converting drivers to Kconfig which use this config
374# option (mxc_nand, ndfc, omap_gpmc).
375config SYS_NAND_BUSWIDTH_16BIT
376 bool "Use 16-bit NAND interface"
377 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
378 help
379 Indicates that NAND device has 16-bit wide data-bus. In absence of this
380 config, bus-width of NAND device is assumed to be either 8-bit and later
381 determined by reading ONFI params.
382 Above config is useful when NAND device's bus-width information cannot
383 be determined from on-chip ONFI params, like in following scenarios:
384 - SPL boot does not support reading of ONFI parameters. This is done to
385 keep SPL code foot-print small.
386 - In current U-Boot flow using nand_init(), driver initialization
387 happens in board_nand_init() which is called before any device probe
388 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
389 not available while configuring controller. So a static CONFIG_NAND_xx
390 is needed to know the device's bus-width in advance.
391
T Karthik Reddy7cd85222018-12-03 16:11:58 +0530392config SYS_NAND_MAX_CHIPS
393 int "NAND max chips"
394 default 1
395 depends on NAND_ARASAN
396 help
397 The maximum number of NAND chips per device to be supported.
398
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200399if SPL
400
401config SYS_NAND_U_BOOT_LOCATIONS
402 bool "Define U-boot binaries locations in NAND"
403 help
404 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
405 This option should not be enabled when compiling U-boot for boards
406 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
407 file.
408
409config SYS_NAND_U_BOOT_OFFS
410 hex "Location in NAND to read U-Boot from"
411 default 0x800000 if NAND_SUNXI
412 depends on SYS_NAND_U_BOOT_LOCATIONS
413 help
414 Set the offset from the start of the nand where u-boot should be
415 loaded from.
416
417config SYS_NAND_U_BOOT_OFFS_REDUND
418 hex "Location in NAND to read U-Boot from"
419 default SYS_NAND_U_BOOT_OFFS
420 depends on SYS_NAND_U_BOOT_LOCATIONS
421 help
422 Set the offset from the start of the nand where the redundant u-boot
423 should be loaded from.
424
425config SPL_NAND_AM33XX_BCH
426 bool "Enables SPL-NAND driver which supports ELM based"
427 depends on NAND_OMAP_GPMC && !OMAP34XX
428 default y
429 help
430 Hardware ECC correction. This is useful for platforms which have ELM
431 hardware engine and use NAND boot mode.
432 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
433 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
434 SPL-NAND driver with software ECC correction support.
435
436config SPL_NAND_DENALI
437 bool "Support Denali NAND controller for SPL"
438 help
439 This is a small implementation of the Denali NAND controller
440 for use on SPL.
441
Masahiro Yamada64648cb2020-04-17 16:51:42 +0900442config NAND_DENALI_SPARE_AREA_SKIP_BYTES
443 int "Number of bytes skipped in OOB area"
444 depends on SPL_NAND_DENALI
445 range 0 63
446 help
447 This option specifies the number of bytes to skip from the beginning
448 of OOB area before last ECC sector data starts. This is potentially
449 used to preserve the bad block marker in the OOB area.
450
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200451config SPL_NAND_SIMPLE
452 bool "Use simple SPL NAND driver"
453 depends on !SPL_NAND_AM33XX_BCH
454 help
455 Support for NAND boot using simple NAND drivers that
456 expose the cmd_ctrl() interface.
457endif
458
459endif # if NAND