Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / e7f3959a66e603c63a377adcd2733120f84a407d / . / dts / upstream / src / arm64 / ti / k3-j721e-sk.dts
blob: 0c4575ad8d7cb03919a7a4520acc2d4059a23287 [file] [log] [blame]
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only OR MIT
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2/*
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]3 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4 *
5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
6 */
7
8/dts-v1/;
9
10#include "k3-j721e.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/net/ti-dp83867.h>
14
15/ {
16 compatible = "ti,j721e-sk", "ti,j721e";
17 model = "Texas Instruments J721E SK";
18
19 aliases {
20 serial0 = &wkup_uart0;
21 serial1 = &mcu_uart0;
22 serial2 = &main_uart0;
23 serial3 = &main_uart1;
24 ethernet0 = &cpsw_port1;
25 mmc1 = &main_sdhci1;
26 };
27
28 chosen {
29 stdout-path = "serial2:115200n8";
30 };
31
32 memory@80000000 {
33 device_type = "memory";
34 /* 4G RAM */
35 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
36 <0x00000008 0x80000000 0x00000000 0x80000000>;
37 };
38
39 reserved_memory: reserved-memory {
40 #address-cells = <2>;
41 #size-cells = <2>;
42 ranges;
43
44 secure_ddr: optee@9e800000 {
45 reg = <0x00 0x9e800000 0x00 0x01800000>;
46 alignment = <0x1000>;
47 no-map;
48 };
49
50 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
51 compatible = "shared-dma-pool";
52 reg = <0x00 0xa0000000 0x00 0x100000>;
53 no-map;
54 };
55
56 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
57 compatible = "shared-dma-pool";
58 reg = <0x00 0xa0100000 0x00 0xf00000>;
59 no-map;
60 };
61
62 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
63 compatible = "shared-dma-pool";
64 reg = <0x00 0xa1000000 0x00 0x100000>;
65 no-map;
66 };
67
68 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
69 compatible = "shared-dma-pool";
70 reg = <0x00 0xa1100000 0x00 0xf00000>;
71 no-map;
72 };
73
74 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
75 compatible = "shared-dma-pool";
76 reg = <0x00 0xa2000000 0x00 0x100000>;
77 no-map;
78 };
79
80 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
81 compatible = "shared-dma-pool";
82 reg = <0x00 0xa2100000 0x00 0xf00000>;
83 no-map;
84 };
85
86 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
87 compatible = "shared-dma-pool";
88 reg = <0x00 0xa3000000 0x00 0x100000>;
89 no-map;
90 };
91
92 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
93 compatible = "shared-dma-pool";
94 reg = <0x00 0xa3100000 0x00 0xf00000>;
95 no-map;
96 };
97
98 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
99 compatible = "shared-dma-pool";
100 reg = <0x00 0xa4000000 0x00 0x100000>;
101 no-map;
102 };
103
104 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
105 compatible = "shared-dma-pool";
106 reg = <0x00 0xa4100000 0x00 0xf00000>;
107 no-map;
108 };
109
110 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
111 compatible = "shared-dma-pool";
112 reg = <0x00 0xa5000000 0x00 0x100000>;
113 no-map;
114 };
115
116 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
117 compatible = "shared-dma-pool";
118 reg = <0x00 0xa5100000 0x00 0xf00000>;
119 no-map;
120 };
121
122 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
123 compatible = "shared-dma-pool";
124 reg = <0x00 0xa6000000 0x00 0x100000>;
125 no-map;
126 };
127
128 c66_0_memory_region: c66-memory@a6100000 {
129 compatible = "shared-dma-pool";
130 reg = <0x00 0xa6100000 0x00 0xf00000>;
131 no-map;
132 };
133
134 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
135 compatible = "shared-dma-pool";
136 reg = <0x00 0xa7000000 0x00 0x100000>;
137 no-map;
138 };
139
140 c66_1_memory_region: c66-memory@a7100000 {
141 compatible = "shared-dma-pool";
142 reg = <0x00 0xa7100000 0x00 0xf00000>;
143 no-map;
144 };
145
146 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
147 compatible = "shared-dma-pool";
148 reg = <0x00 0xa8000000 0x00 0x100000>;
149 no-map;
150 };
151
152 c71_0_memory_region: c71-memory@a8100000 {
153 compatible = "shared-dma-pool";
154 reg = <0x00 0xa8100000 0x00 0xf00000>;
155 no-map;
156 };
157
158 rtos_ipc_memory_region: ipc-memories@aa000000 {
159 reg = <0x00 0xaa000000 0x00 0x01c00000>;
160 alignment = <0x1000>;
161 no-map;
162 };
163 };
164
165 vusb_main: fixedregulator-vusb-main5v0 {
166 /* USB MAIN INPUT 5V DC */
167 compatible = "regulator-fixed";
168 regulator-name = "vusb-main5v0";
169 regulator-min-microvolt = <5000000>;
170 regulator-max-microvolt = <5000000>;
171 regulator-always-on;
172 regulator-boot-on;
173 };
174
175 vsys_3v3: fixedregulator-vsys3v3 {
176 /* Output of LM5141 */
177 compatible = "regulator-fixed";
178 regulator-name = "vsys_3v3";
179 regulator-min-microvolt = <3300000>;
180 regulator-max-microvolt = <3300000>;
181 vin-supply = <&vusb_main>;
182 regulator-always-on;
183 regulator-boot-on;
184 };
185
186 vdd_mmc1: fixedregulator-sd {
187 compatible = "regulator-fixed";
188 pinctrl-names = "default";
189 pinctrl-0 = <&vdd_mmc1_en_pins_default>;
190 regulator-name = "vdd_mmc1";
191 regulator-min-microvolt = <3300000>;
192 regulator-max-microvolt = <3300000>;
193 regulator-boot-on;
194 enable-active-high;
195 vin-supply = <&vsys_3v3>;
196 gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>;
197 };
198
199 vdd_sd_dv_alt: gpio-regulator-tps659411 {
200 compatible = "regulator-gpio";
201 pinctrl-names = "default";
202 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
203 regulator-name = "tps659411";
204 regulator-min-microvolt = <1800000>;
205 regulator-max-microvolt = <3300000>;
206 regulator-boot-on;
207 vin-supply = <&vsys_3v3>;
208 gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>;
209 states = <1800000 0x0>,
210 <3300000 0x1>;
211 };
212
213 dp_pwr_3v3: fixedregulator-dp-prw {
214 compatible = "regulator-fixed";
215 regulator-name = "dp-pwr";
216 regulator-min-microvolt = <3300000>;
217 regulator-max-microvolt = <3300000>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&dp_pwr_en_pins_default>;
220 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */
221 enable-active-high;
222 };
223
224 dp0: connector {
225 compatible = "dp-connector";
226 label = "DP0";
227 type = "full-size";
228 dp-pwr-supply = <&dp_pwr_3v3>;
229
230 port {
231 dp_connector_in: endpoint {
232 remote-endpoint = <&dp0_out>;
233 };
234 };
235 };
236
237 hdmi-connector {
238 compatible = "hdmi-connector";
239 label = "hdmi";
240 type = "a";
241
242 pinctrl-names = "default";
243 pinctrl-0 = <&hdmi_hpd_pins_default>;
244
245 ddc-i2c-bus = <&main_i2c1>;
246
247 /* HDMI_HPD */
248 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>;
249
250 port {
251 hdmi_connector_in: endpoint {
252 remote-endpoint = <&tfp410_out>;
253 };
254 };
255 };
256
257 dvi-bridge {
258 compatible = "ti,tfp410";
259
260 pinctrl-names = "default";
261 pinctrl-0 = <&hdmi_pdn_pins_default>;
262
263 powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>;
264 ti,deskew = <0>;
265
266 ports {
267 #address-cells = <1>;
268 #size-cells = <0>;
269
270 port@0 {
271 reg = <0>;
272
273 tfp410_in: endpoint {
274 remote-endpoint = <&dpi1_out>;
275 pclk-sample = <1>;
276 };
277 };
278
279 port@1 {
280 reg = <1>;
281
282 tfp410_out: endpoint {
283 remote-endpoint =
284 <&hdmi_connector_in>;
285 };
286 };
287 };
288 };
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]289
290 csi_mux: mux-controller {
291 compatible = "gpio-mux";
292 #mux-state-cells = <1>;
293 mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>;
294 idle-state = <0>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&main_csi_mux_sel_pins_default>;
297 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]298};
299
300&main_pmx0 {
301 main_mmc1_pins_default: main-mmc1-default-pins {
302 pinctrl-single,pins = <
303 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
304 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
305 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
306 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
307 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
308 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
309 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
310 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
311 >;
312 };
313
314 main_uart0_pins_default: main-uart0-default-pins {
315 pinctrl-single,pins = <
316 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
317 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
318 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
319 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
320 >;
321 };
322
323 main_uart1_pins_default: main-uart1-default-pins {
324 pinctrl-single,pins = <
325 J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
326 J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
327 >;
328 };
329
330 main_i2c0_pins_default: main-i2c0-default-pins {
331 pinctrl-single,pins = <
332 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
333 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
334 >;
335 };
336
337 main_i2c1_pins_default: main-i2c1-default-pins {
338 pinctrl-single,pins = <
339 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
340 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
341 >;
342 };
343
344 main_i2c3_pins_default: main-i2c3-default-pins {
345 pinctrl-single,pins = <
346 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
347 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
348 >;
349 };
350
351 main_usbss0_pins_default: main-usbss0-default-pins {
352 pinctrl-single,pins = <
353 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
354 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
355 >;
356 };
357
358 main_usbss1_pins_default: main-usbss1-default-pins {
359 pinctrl-single,pins = <
360 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
361 >;
362 };
363
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]364 main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins {
365 pinctrl-single,pins = <
366 J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */
367 >;
368 };
369
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]370 dp0_pins_default: dp0-default-pins {
371 pinctrl-single,pins = <
372 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
373 >;
374 };
375
376 dp_pwr_en_pins_default: dp-pwr-en-default-pins {
377 pinctrl-single,pins = <
378 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
379 >;
380 };
381
382 dss_vout0_pins_default: dss-vout0-default-pins {
383 pinctrl-single,pins = <
384 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
385 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
386 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
387 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
388 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
389 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
390 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
391 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
392 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
393 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
394 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
395 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
396 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
397 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
398 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
399 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
400 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
401 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
402 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
403 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
404 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
405 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
406 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
407 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
408 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
409 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
410 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
411 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
412 >;
413 };
414
415 hdmi_hpd_pins_default: hdmi-hpd-default-pins {
416 pinctrl-single,pins = <
417 J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */
418 >;
419 };
420
421 hdmi_pdn_pins_default: hdmi-pdn-default-pins {
422 pinctrl-single,pins = <
423 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
424 >;
425 };
426
427 /* Reset for M.2 E Key slot on PCIe0 */
428 ekey_reset_pins_default: ekey-reset-pns-default-pins {
429 pinctrl-single,pins = <
430 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */
431 >;
432 };
433
434 main_i2c5_pins_default: main-i2c5-default-pins {
435 pinctrl-single,pins = <
436 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
437 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
438 >;
439 };
440
441 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
442 pinctrl-single,pins = <
443 J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
444 J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */
445 J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
446 J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
447 J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
448 J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
449 J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
450 J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
451 J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
452 J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
453 J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
454 J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
455 J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
456 J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
457 J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
458 J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
459 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
460 J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
461 J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
462 J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
463 J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
464 J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
465 J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
466 >;
467 };
468
469 rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins {
470 pinctrl-single,pins = <
471 J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */
472 >;
473 };
474};
475
476&wkup_pmx0 {
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]477 pmic_irq_pins_default: pmic-irq-default-pins {
478 pinctrl-single,pins = <
479 J721E_WKUP_IOPAD(0x0cc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
480 >;
481 };
482
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]483 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
484 pinctrl-single,pins = <
485 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
486 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
487 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
488 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
489 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
490 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
491 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
492 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
493 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
494 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
495 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
496 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
497 >;
498 };
499
500 mcu_mdio_pins_default: mcu-mdio1-default-pins {
501 pinctrl-single,pins = <
502 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
503 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
504 >;
505 };
506
507 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
508 pinctrl-single,pins = <
509 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
510 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
511 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
512 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
513 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
514 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
515 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
516 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
517 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
518 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
519 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
520 >;
521 };
522
523 vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
524 pinctrl-single,pins = <
525 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
526 >;
527 };
528
529 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
530 pinctrl-single,pins = <
531 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
532 >;
533 };
534
535 wkup_uart0_pins_default: wkup-uart0-default-pins {
536 pinctrl-single,pins = <
537 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
538 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
539 >;
540 };
541
542 mcu_uart0_pins_default: mcu-uart0-default-pins {
543 pinctrl-single,pins = <
544 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
545 J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
546 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
547 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
548 >;
549 };
550
551 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
552 pinctrl-single,pins = <
553 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
554 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
555 >;
556 };
557
558 /* Reset for M.2 M Key slot on PCIe1 */
559 mkey_reset_pins_default: mkey-reset-pns-default-pins {
560 pinctrl-single,pins = <
561 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */
562 >;
563 };
564};
565
566&wkup_uart0 {
567 /* Wakeup UART is used by System firmware */
568 status = "reserved";
569 pinctrl-names = "default";
570 pinctrl-0 = <&wkup_uart0_pins_default>;
571};
572
573&wkup_i2c0 {
574 status = "okay";
575 pinctrl-names = "default";
576 pinctrl-0 = <&wkup_i2c0_pins_default>;
577 clock-frequency = <400000>;
578
579 eeprom@51 {
580 /* AT24C512C-MAHM-T */
581 compatible = "atmel,24c512";
582 reg = <0x51>;
583 };
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]584
585 tps659413: pmic@48 {
586 compatible = "ti,tps6594-q1";
587 reg = <0x48>;
588 system-power-controller;
589 pinctrl-names = "default";
590 pinctrl-0 = <&pmic_irq_pins_default>;
591 interrupt-parent = <&wkup_gpio0>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]592 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]593 gpio-controller;
594 #gpio-cells = <2>;
595 ti,primary-pmic;
596 buck123-supply = <&vsys_3v3>;
597 buck4-supply = <&vsys_3v3>;
598 buck5-supply = <&vsys_3v3>;
599 ldo1-supply = <&vsys_3v3>;
600 ldo2-supply = <&vsys_3v3>;
601 ldo3-supply = <&vsys_3v3>;
602 ldo4-supply = <&vsys_3v3>;
603
604 regulators {
605 bucka123: buck123 {
606 regulator-name = "vdd_cpu_avs";
607 regulator-min-microvolt = <600000>;
608 regulator-max-microvolt = <900000>;
609 regulator-boot-on;
610 regulator-always-on;
611 bootph-pre-ram;
612 };
613
614 bucka4: buck4 {
615 regulator-name = "vdd_mcu_0v85";
616 regulator-min-microvolt = <850000>;
617 regulator-max-microvolt = <850000>;
618 regulator-boot-on;
619 regulator-always-on;
620 };
621
622 bucka5: buck5 {
623 regulator-name = "vdd_phyio_1v8";
624 regulator-min-microvolt = <1800000>;
625 regulator-max-microvolt = <1800000>;
626 regulator-boot-on;
627 regulator-always-on;
628 };
629
630 ldoa1: ldo1 {
631 regulator-name = "vdd1_lpddr4_1v8";
632 regulator-min-microvolt = <1800000>;
633 regulator-max-microvolt = <1800000>;
634 regulator-boot-on;
635 regulator-always-on;
636 };
637
638 ldoa2: ldo2 {
639 regulator-name = "vdd_mcuio_1v8";
640 regulator-min-microvolt = <1800000>;
641 regulator-max-microvolt = <1800000>;
642 regulator-boot-on;
643 regulator-always-on;
644 };
645
646 ldoa3: ldo3 {
647 regulator-name = "vdda_dll_0v8";
648 regulator-min-microvolt = <800000>;
649 regulator-max-microvolt = <800000>;
650 regulator-boot-on;
651 regulator-always-on;
652 };
653
654 ldoa4: ldo4 {
655 regulator-name = "vda_mcu_1v8";
656 regulator-min-microvolt = <1800000>;
657 regulator-max-microvolt = <1800000>;
658 regulator-boot-on;
659 regulator-always-on;
660 };
661 };
662 };
663
664 tps659411: pmic@4c {
665 compatible = "ti,tps6594-q1";
666 reg = <0x4c>;
667 system-power-controller;
668 interrupt-parent = <&wkup_gpio0>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]669 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]670 gpio-controller;
671 #gpio-cells = <2>;
672 buck1234-supply = <&vsys_3v3>;
673 buck5-supply = <&vsys_3v3>;
674 ldo1-supply = <&vsys_3v3>;
675 ldo2-supply = <&vsys_3v3>;
676 ldo3-supply = <&vsys_3v3>;
677 ldo4-supply = <&vsys_3v3>;
678
679 regulators {
680 buckb1234: buck1234 {
681 regulator-name = "vdd_core_0v8";
682 regulator-min-microvolt = <800000>;
683 regulator-max-microvolt = <800000>;
684 regulator-boot-on;
685 regulator-always-on;
686 };
687
688 buckb5: buck5 {
689 regulator-name = "vdd_ram_0v85";
690 regulator-min-microvolt = <850000>;
691 regulator-max-microvolt = <850000>;
692 regulator-boot-on;
693 regulator-always-on;
694 };
695
696 ldob1: ldo1 {
697 regulator-name = "vdd_sd_dv";
698 regulator-min-microvolt = <1800000>;
699 regulator-max-microvolt = <3300000>;
700 regulator-boot-on;
701 regulator-always-on;
702 };
703
704 ldob2: ldo2 {
705 regulator-name = "vdd_usb_3v3";
706 regulator-min-microvolt = <3300000>;
707 regulator-max-microvolt = <3300000>;
708 regulator-boot-on;
709 regulator-always-on;
710 };
711
712 ldob3: ldo3 {
713 regulator-name = "vdd_io_1v8";
714 regulator-min-microvolt = <1800000>;
715 regulator-max-microvolt = <1800000>;
716 regulator-boot-on;
717 regulator-always-on;
718 };
719
720 ldob4: ldo4 {
721 regulator-name = "vda_pll_1v8";
722 regulator-min-microvolt = <1800000>;
723 regulator-max-microvolt = <1800000>;
724 regulator-boot-on;
725 regulator-always-on;
726 };
727 };
728 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]729};
730
731&mcu_uart0 {
732 status = "okay";
733 pinctrl-names = "default";
734 pinctrl-0 = <&mcu_uart0_pins_default>;
735};
736
737&main_uart0 {
738 status = "okay";
739 pinctrl-names = "default";
740 pinctrl-0 = <&main_uart0_pins_default>;
741 /* Shared with ATF on this platform */
742 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
743};
744
745&main_uart1 {
746 status = "okay";
747 pinctrl-names = "default";
748 pinctrl-0 = <&main_uart1_pins_default>;
749};
750
751&main_sdhci1 {
752 /* SD Card */
753 status = "okay";
754 vmmc-supply = <&vdd_mmc1>;
755 vqmmc-supply = <&vdd_sd_dv_alt>;
756 pinctrl-names = "default";
757 pinctrl-0 = <&main_mmc1_pins_default>;
758 ti,driver-strength-ohm = <50>;
759 disable-wp;
760};
761
762&ospi0 {
763 status = "okay";
764 pinctrl-names = "default";
765 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
766
767 flash@0 {
768 compatible = "jedec,spi-nor";
769 reg = <0x0>;
770 spi-tx-bus-width = <8>;
771 spi-rx-bus-width = <8>;
772 spi-max-frequency = <25000000>;
773 cdns,tshsl-ns = <60>;
774 cdns,tsd2d-ns = <60>;
775 cdns,tchsh-ns = <60>;
776 cdns,tslch-ns = <60>;
777 cdns,read-delay = <4>;
778
779 partitions {
780 compatible = "fixed-partitions";
781 #address-cells = <1>;
782 #size-cells = <1>;
783
784 partition@0 {
785 label = "ospi.tiboot3";
786 reg = <0x0 0x80000>;
787 };
788
789 partition@80000 {
790 label = "ospi.tispl";
791 reg = <0x80000 0x200000>;
792 };
793
794 partition@280000 {
795 label = "ospi.u-boot";
796 reg = <0x280000 0x400000>;
797 };
798
799 partition@680000 {
800 label = "ospi.env";
801 reg = <0x680000 0x40000>;
802 };
803
804 partition@6c0000 {
805 label = "ospi.sysfw";
806 reg = <0x6c0000 0x100000>;
807 };
808
809 partition@7c0000 {
810 label = "ospi.env.backup";
811 reg = <0x7c0000 0x40000>;
812 };
813
814 partition@800000 {
815 label = "ospi.rootfs";
816 reg = <0x800000 0x37c0000>;
817 };
818
819 partition@3fc0000 {
820 label = "ospi.phypattern";
821 reg = <0x3fc0000 0x40000>;
822 };
823 };
824 };
825};
826
827&main_i2c0 {
828 status = "okay";
829 pinctrl-names = "default";
830 pinctrl-0 = <&main_i2c0_pins_default>;
831 clock-frequency = <400000>;
832
833 i2c-mux@71 {
834 compatible = "nxp,pca9543";
835 #address-cells = <1>;
836 #size-cells = <0>;
837 reg = <0x71>;
838
839 /* PCIe1 M.2 M Key I2C */
840 i2c@0 {
841 #address-cells = <1>;
842 #size-cells = <0>;
843 reg = <0>;
844 };
845
846 /* PCIe0 M.2 E Key I2C */
847 i2c@1 {
848 #address-cells = <1>;
849 #size-cells = <0>;
850 reg = <1>;
851 };
852 };
853};
854
855&main_i2c1 {
856 status = "okay";
857 pinctrl-names = "default";
858 pinctrl-0 = <&main_i2c1_pins_default>;
859 /* i2c1 is used for DVI DDC, so we need to use 100kHz */
860 clock-frequency = <100000>;
861};
862
863&main_i2c3 {
864 status = "okay";
865 pinctrl-names = "default";
866 pinctrl-0 = <&main_i2c3_pins_default>;
867 clock-frequency = <400000>;
868
869 i2c-mux@70 {
870 compatible = "nxp,pca9543";
871 #address-cells = <1>;
872 #size-cells = <0>;
873 reg = <0x70>;
874
875 /* CSI0 I2C */
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]876 cam0_i2c: i2c@0 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]877 #address-cells = <1>;
878 #size-cells = <0>;
879 reg = <0>;
880 };
881
882 /* CSI1 I2C */
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]883 cam1_i2c: i2c@1 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]884 #address-cells = <1>;
885 #size-cells = <0>;
886 reg = <1>;
887 };
888 };
889};
890
891&main_i2c5 {
892 /* Brought out on RPi Header */
893 status = "okay";
894 pinctrl-names = "default";
895 pinctrl-0 = <&main_i2c5_pins_default>;
896 clock-frequency = <400000>;
897};
898
899&main_gpio0 {
900 status = "okay";
901 pinctrl-names = "default";
902 pinctrl-0 = <&rpi_header_gpio0_pins_default>;
903};
904
905&main_gpio1 {
906 status = "okay";
907 pinctrl-names = "default";
908 pinctrl-0 = <&rpi_header_gpio1_pins_default>;
909};
910
911&wkup_gpio0 {
912 status = "okay";
913};
914
915&usb_serdes_mux {
916 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
917};
918
919&serdes_ln_ctrl {
920 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
921 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
922 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
923 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
924 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
925 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
926};
927
928&serdes_wiz3 {
929 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
930 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
931};
932
933&serdes3 {
934 serdes3_usb_link: phy@0 {
935 reg = <0>;
936 cdns,num-lanes = <2>;
937 #phy-cells = <0>;
938 cdns,phy-type = <PHY_TYPE_USB3>;
939 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
940 };
941};
942
943&serdes4 {
944 torrent_phy_dp: phy@0 {
945 reg = <0>;
946 resets = <&serdes_wiz4 1>;
947 cdns,phy-type = <PHY_TYPE_DP>;
948 cdns,num-lanes = <4>;
949 cdns,max-bit-rate = <5400>;
950 #phy-cells = <0>;
951 };
952};
953
954&mhdp {
955 phys = <&torrent_phy_dp>;
956 phy-names = "dpphy";
957 pinctrl-names = "default";
958 pinctrl-0 = <&dp0_pins_default>;
959};
960
961&usbss0 {
962 pinctrl-names = "default";
963 pinctrl-0 = <&main_usbss0_pins_default>;
964 ti,vbus-divider;
965};
966
967&usb0 {
968 dr_mode = "otg";
969 maximum-speed = "super-speed";
970 phys = <&serdes3_usb_link>;
971 phy-names = "cdns3,usb3-phy";
972};
973
974&serdes2 {
975 serdes2_usb_link: phy@1 {
976 reg = <1>;
977 cdns,num-lanes = <1>;
978 #phy-cells = <0>;
979 cdns,phy-type = <PHY_TYPE_USB3>;
980 resets = <&serdes_wiz2 2>;
981 };
982};
983
984&usbss1 {
985 pinctrl-names = "default";
986 pinctrl-0 = <&main_usbss1_pins_default>;
987 ti,vbus-divider;
988};
989
990&usb1 {
991 dr_mode = "host";
992 maximum-speed = "super-speed";
993 phys = <&serdes2_usb_link>;
994 phy-names = "cdns3,usb3-phy";
995};
996
997&mcu_cpsw {
998 pinctrl-names = "default";
999 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
1000};
1001
1002&davinci_mdio {
1003 phy0: ethernet-phy@0 {
1004 reg = <0>;
1005 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
1006 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
1007 };
1008};
1009
1010&cpsw_port1 {
1011 phy-mode = "rgmii-rxid";
1012 phy-handle = <&phy0>;
1013};
1014
1015&dss {
1016 pinctrl-names = "default";
1017 pinctrl-0 = <&dss_vout0_pins_default>;
1018
1019 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
1020 <&k3_clks 152 4>, /* VP 2 pixel clock */
1021 <&k3_clks 152 9>, /* VP 3 pixel clock */
1022 <&k3_clks 152 13>; /* VP 4 pixel clock */
1023 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
1024 <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */
1025 <&k3_clks 152 11>, /* PLL18_HSDIV0 */
1026 <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */
1027};
1028
1029&dss_ports {
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1032
1033 port@0 {
1034 reg = <0>;
1035
1036 dpi0_out: endpoint {
1037 remote-endpoint = <&dp0_in>;
1038 };
1039 };
1040
1041 port@1 {
1042 reg = <1>;
1043
1044 dpi1_out: endpoint {
1045 remote-endpoint = <&tfp410_in>;
1046 };
1047 };
1048};
1049
1050&dp0_ports {
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1053
1054 port@0 {
1055 reg = <0>;
1056 dp0_in: endpoint {
1057 remote-endpoint = <&dpi0_out>;
1058 };
1059 };
1060
1061 port@4 {
1062 reg = <4>;
1063 dp0_out: endpoint {
1064 remote-endpoint = <&dp_connector_in>;
1065 };
1066 };
1067};
1068
1069&serdes0 {
1070 serdes0_pcie_link: phy@0 {
1071 reg = <0>;
1072 cdns,num-lanes = <1>;
1073 #phy-cells = <0>;
1074 cdns,phy-type = <PHY_TYPE_PCIE>;
1075 resets = <&serdes_wiz0 1>;
1076 };
1077};
1078
1079&serdes1 {
1080 serdes1_pcie_link: phy@0 {
1081 reg = <0>;
1082 cdns,num-lanes = <2>;
1083 #phy-cells = <0>;
1084 cdns,phy-type = <PHY_TYPE_PCIE>;
1085 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
1086 };
1087};
1088
1089&pcie0_rc {
1090 status = "okay";
1091 pinctrl-names = "default";
1092 pinctrl-0 = <&ekey_reset_pins_default>;
1093 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>;
1094
1095 phys = <&serdes0_pcie_link>;
1096 phy-names = "pcie-phy";
1097 num-lanes = <1>;
1098};
1099
1100&pcie1_rc {
1101 status = "okay";
1102 pinctrl-names = "default";
1103 pinctrl-0 = <&mkey_reset_pins_default>;
1104 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
1105
1106 phys = <&serdes1_pcie_link>;
1107 phy-names = "pcie-phy";
1108 num-lanes = <2>;
1109};
1110
1111&ufs_wrapper {
1112 status = "disabled";
1113};
1114
1115&mailbox0_cluster0 {
1116 status = "okay";
1117 interrupts = <436>;
1118
1119 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
1120 ti,mbox-rx = <0 0 0>;
1121 ti,mbox-tx = <1 0 0>;
1122 };
1123
1124 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
1125 ti,mbox-rx = <2 0 0>;
1126 ti,mbox-tx = <3 0 0>;
1127 };
1128};
1129
1130&mailbox0_cluster1 {
1131 status = "okay";
1132 interrupts = <432>;
1133
1134 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
1135 ti,mbox-rx = <0 0 0>;
1136 ti,mbox-tx = <1 0 0>;
1137 };
1138
1139 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
1140 ti,mbox-rx = <2 0 0>;
1141 ti,mbox-tx = <3 0 0>;
1142 };
1143};
1144
1145&mailbox0_cluster2 {
1146 status = "okay";
1147 interrupts = <428>;
1148
1149 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
1150 ti,mbox-rx = <0 0 0>;
1151 ti,mbox-tx = <1 0 0>;
1152 };
1153
1154 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
1155 ti,mbox-rx = <2 0 0>;
1156 ti,mbox-tx = <3 0 0>;
1157 };
1158};
1159
1160&mailbox0_cluster3 {
1161 status = "okay";
1162 interrupts = <424>;
1163
1164 mbox_c66_0: mbox-c66-0 {
1165 ti,mbox-rx = <0 0 0>;
1166 ti,mbox-tx = <1 0 0>;
1167 };
1168
1169 mbox_c66_1: mbox-c66-1 {
1170 ti,mbox-rx = <2 0 0>;
1171 ti,mbox-tx = <3 0 0>;
1172 };
1173};
1174
1175&mailbox0_cluster4 {
1176 status = "okay";
1177 interrupts = <420>;
1178
1179 mbox_c71_0: mbox-c71-0 {
1180 ti,mbox-rx = <0 0 0>;
1181 ti,mbox-tx = <1 0 0>;
1182 };
1183};
1184
1185&mcu_r5fss0_core0 {
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1186 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1187 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
1188 <&mcu_r5fss0_core0_memory_region>;
1189};
1190
1191&mcu_r5fss0_core1 {
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1192 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1193 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
1194 <&mcu_r5fss0_core1_memory_region>;
1195};
1196
1197&main_r5fss0_core0 {
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1198 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1199 memory-region = <&main_r5fss0_core0_dma_memory_region>,
1200 <&main_r5fss0_core0_memory_region>;
1201};
1202
1203&main_r5fss0_core1 {
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1204 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1205 memory-region = <&main_r5fss0_core1_dma_memory_region>,
1206 <&main_r5fss0_core1_memory_region>;
1207};
1208
1209&main_r5fss1_core0 {
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1210 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1211 memory-region = <&main_r5fss1_core0_dma_memory_region>,
1212 <&main_r5fss1_core0_memory_region>;
1213};
1214
1215&main_r5fss1_core1 {
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1216 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1217 memory-region = <&main_r5fss1_core1_dma_memory_region>,
1218 <&main_r5fss1_core1_memory_region>;
1219};
1220
1221&c66_0 {
1222 status = "okay";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1223 mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1224 memory-region = <&c66_0_dma_memory_region>,
1225 <&c66_0_memory_region>;
1226};
1227
1228&c66_1 {
1229 status = "okay";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1230 mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1231 memory-region = <&c66_1_dma_memory_region>,
1232 <&c66_1_memory_region>;
1233};
1234
1235&c71_0 {
1236 status = "okay";
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]1237 mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1238 memory-region = <&c71_0_dma_memory_region>,
1239 <&c71_0_memory_region>;
1240};