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git01.mediatek.com / filogic / uboot / e7eaf6291eac8dc1111ba1b15974b7fedb587d06 / . / board / mpr2 / lowlevel_init.S
blob: 5246b63365edbaef06e1ee51e545c29658e42e9e [file] [log] [blame]
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]1/*
2 * (C) Copyright 2008
3 * Mark Jonas <mark.jonas@de.bosch.com>
4 *
5 * (C) Copyright 2007
6 * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * board/mpr2/lowlevel_init.S
9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]10 * SPDX-License-Identifier: GPL-2.0+
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]11 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]12#include <asm/macro.h>
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]13
14 .global lowlevel_init
15
16 .text
17 .align 2
18
19lowlevel_init:
20
21/*
22 * Set frequency multipliers and dividers in FRQCR.
23 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]24 write16 WTCSR_A, WTCSR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]25
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]26 write16 WTCNT_A, WTCNT_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]27
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]28 write16 FRQCR_A, FRQCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]29
30/*
31 * Setup CS0 (Flash).
32 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]33 write32 CS0BCR_A, CS0BCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]34
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]35 write32 CS0WCR_A, CS0WCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]36
37/*
38 * Setup CS3 (SDRAM).
39 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]40 write32 CS3BCR_A, CS3BCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]41
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]42 write32 CS3WCR_A, CS3WCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]43
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]44 write32 SDCR_A, SDCR_D1
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]45
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]46 write32 RTCSR_A, RTCSR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]47
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]48 write32 RTCNT_A, RTCNT_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]49
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]50 write32 RTCOR_A, RTCOR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]51
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]52 write32 SDCR_A, SDCR_D2
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]53
54 mov.l SDMR3_A, r1
55 mov.l SDMR3_D, r0
56 add r0, r1
57 mov #0, r0
58 mov.w r0, @r1
59
60 rts
61 nop
62
63 .align 4
64
65/*
66 * Configuration for MPR2 A.3 through A.7
67 */
68
69/*
70 * PLL Settings
71 */
Nobuhiro Iwamatsu471e0ec2010-07-22 16:20:08 +0900[diff] [blame]72FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
73WTCNT_D: .word 0x5A00 /* start counting at zero */
74WTCSR_D: .word 0xA507 /* divide by 4096 */
75.align 2
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]76/*
77 * Spansion S29GL256N11 @ 48 MHz
78 */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]79/* 1 idle cycle inserted, normal space, 16 bit */
80CS0BCR_D: .long 0x12490400
81/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
82CS0WCR_D: .long 0x00000340
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]83
84/*
85 * Samsung K4S511632B-UL75 @ 48 MHz
86 * Micron MT48LC32M16A2-75 @ 48 MHz
87 */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]88/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
89CS3BCR_D: .long 0x10004400
90/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
91CS3WCR_D: .long 0x00000091
92/* no refresh, 13 rows, 10 cols, NO bank active mode */
93SDCR_D1: .long 0x00000012
94SDCR_D2: .long 0x00000812 /* refresh */
95RTCSR_D: .long 0xA55A0008 /* 1/4, once */
96RTCNT_D: .long 0xA55A005D /* count 93 */
97RTCOR_D: .long 0xa55a005d /* count 93 */
98/* mode register CL2, burst read and SINGLE WRITE */
99SDMR3_D: .long 0x440
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]100
101/*
102 * Registers
103 */
104
105FRQCR_A: .long 0xA415FF80
106WTCNT_A: .long 0xA415FF84
107WTCSR_A: .long 0xA415FF86
108
109#define BSC_BASE 0xA4FD0000
110CS0BCR_A: .long BSC_BASE + 0x04
111CS3BCR_A: .long BSC_BASE + 0x0C
112CS0WCR_A: .long BSC_BASE + 0x24
113CS3WCR_A: .long BSC_BASE + 0x2C
114SDCR_A: .long BSC_BASE + 0x44
115RTCSR_A: .long BSC_BASE + 0x48
116RTCNT_A: .long BSC_BASE + 0x4C
117RTCOR_A: .long BSC_BASE + 0x50
118SDMR3_A: .long BSC_BASE + 0x5000