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git01.mediatek.com / filogic / uboot / e7cc796e8e9f1841ea27e06eb7825311e2843bc4 / . / drivers / watchdog / tnetv107x_wdt.c
blob: 3d3f366c021e031c2e06ac76963fbba155cc3b80 [file] [log] [blame]
Cyril Chemparathy692a7af2010-06-07 14:13:32 -0400[diff] [blame]1/*
2 * TNETV107X: Watchdog timer implementation (for reset)
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Cyril Chemparathy692a7af2010-06-07 14:13:32 -0400[diff] [blame]5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/clock.h>
10
11#define MAX_DIV 0xFFFE0001
12
13struct wdt_regs {
14 u32 kick_lock;
15#define KICK_LOCK_1 0x5555
16#define KICK_LOCK_2 0xaaaa
17 u32 kick;
18
19 u32 change_lock;
20#define CHANGE_LOCK_1 0x6666
21#define CHANGE_LOCK_2 0xbbbb
22 u32 change;
23
24 u32 disable_lock;
25#define DISABLE_LOCK_1 0x7777
26#define DISABLE_LOCK_2 0xcccc
27#define DISABLE_LOCK_3 0xdddd
28 u32 disable;
29
30 u32 prescale_lock;
31#define PRESCALE_LOCK_1 0x5a5a
32#define PRESCALE_LOCK_2 0xa5a5
33 u32 prescale;
34};
35
36static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
37
38#define wdt_reg_read(reg) __raw_readl(&regs->reg)
39#define wdt_reg_write(reg, val) __raw_writel((val), &regs->reg)
40
41static int write_prescale_reg(unsigned long prescale_value)
42{
43 wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
44 if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
45 return -1;
46
47 wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
48 if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
49 return -1;
50
51 wdt_reg_write(prescale, prescale_value);
52
53 return 0;
54}
55
56static int write_change_reg(unsigned long initial_timer_value)
57{
58 wdt_reg_write(change_lock, CHANGE_LOCK_1);
59 if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
60 return -1;
61
62 wdt_reg_write(change_lock, CHANGE_LOCK_2);
63 if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
64 return -1;
65
66 wdt_reg_write(change, initial_timer_value);
67
68 return 0;
69}
70
71static int wdt_control(unsigned long disable_value)
72{
73 wdt_reg_write(disable_lock, DISABLE_LOCK_1);
74 if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
75 return -1;
76
77 wdt_reg_write(disable_lock, DISABLE_LOCK_2);
78 if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
79 return -1;
80
81 wdt_reg_write(disable_lock, DISABLE_LOCK_3);
82 if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
83 return -1;
84
85 wdt_reg_write(disable, disable_value);
86 return 0;
87}
88
89static int wdt_set_period(unsigned long msec)
90{
91 unsigned long change_value, count_value;
92 unsigned long prescale_value = 1;
93 unsigned long refclk_khz, maxdiv;
94 int ret;
95
96 refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
97 maxdiv = (MAX_DIV / refclk_khz);
98
99 if ((!msec) || (msec > maxdiv))
100 return -1;
101
102 count_value = refclk_khz * msec;
103 if (count_value > 0xffff) {
104 change_value = count_value / 0xffff + 1;
105 prescale_value = count_value / change_value;
106 } else {
107 change_value = count_value;
108 }
109
110 ret = write_prescale_reg(prescale_value - 1);
111 if (ret)
112 return ret;
113
114 ret = write_change_reg(change_value);
115 if (ret)
116 return ret;
117
118 return 0;
119}
120
121unsigned long last_wdt = -1;
122
123int wdt_start(unsigned long msecs)
124{
125 int ret;
126 ret = wdt_control(0);
127 if (ret)
128 return ret;
129 ret = wdt_set_period(msecs);
130 if (ret)
131 return ret;
132 ret = wdt_control(1);
133 if (ret)
134 return ret;
135 ret = wdt_kick();
136 last_wdt = msecs;
137 return ret;
138}
139
140int wdt_stop(void)
141{
142 last_wdt = -1;
143 return wdt_control(0);
144}
145
146int wdt_kick(void)
147{
148 wdt_reg_write(kick_lock, KICK_LOCK_1);
149 if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
150 return -1;
151
152 wdt_reg_write(kick_lock, KICK_LOCK_2);
153 if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
154 return -1;
155
156 wdt_reg_write(kick, 1);
157 return 0;
158}
159
160void reset_cpu(ulong addr)
161{
162 clk_enable(TNETV107X_LPSC_WDT_ARM);
163 wdt_start(1);
164 wdt_kick();
165}