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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkc4cbd342005-01-09 18:21:42 +00002/*
3 * Configuation settings for the Sentec Cobra Board.
4 *
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
wdenkc4cbd342005-01-09 18:21:42 +00006 */
7
8/* ---
Bin Meng75574052016-02-05 19:30:11 -08009 * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board
wdenkc4cbd342005-01-09 18:21:42 +000010 * Date: 2004-03-29
11 * Author: Florian Schlote
12 *
13 * For a description of configuration options please refer also to the
14 * general u-boot-1.x.x/README file
15 * ---
16 */
17
18/* ---
19 * board/config.h - configuration options, board specific
20 * ---
21 */
22
23#ifndef _CONFIG_COBRA5272_H
24#define _CONFIG_COBRA5272_H
25
26/* ---
wdenkc4cbd342005-01-09 18:21:42 +000027 * Defines processor clock - important for correct timings concerning serial
28 * interface etc.
wdenkc4cbd342005-01-09 18:21:42 +000029 * ---
30 */
31
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020032#define CONFIG_SYS_CLK 66000000
33#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
wdenkc4cbd342005-01-09 18:21:42 +000034
35/* ---
36 * Enable use of Ethernet
37 * ---
38 */
TsiChungLiewcfa2b482007-08-15 19:41:06 -050039#define CONFIG_MCFFEC
wdenkc4cbd342005-01-09 18:21:42 +000040
TsiChungLiewcfa2b482007-08-15 19:41:06 -050041/* Enable Dma Timer */
42#define CONFIG_MCFTMR
wdenkc4cbd342005-01-09 18:21:42 +000043
44/* ---
45 * Define baudrate for UART1 (console output, tftp, ...)
46 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020047 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
wdenkc4cbd342005-01-09 18:21:42 +000048 * interface
49 * ---
50 */
51
TsiChungLiewcfa2b482007-08-15 19:41:06 -050052#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#define CONFIG_SYS_UART_PORT (0)
wdenkc4cbd342005-01-09 18:21:42 +000054
55/* ---
56 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
57 * timeout acc. to your needs
58 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
59 * for 10 sec
60 * ---
61 */
62
63#if 0
64#define CONFIG_WATCHDOG
65#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
66#endif
67
68/* ---
69 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
70 * bootloader residing in flash ('chainloading'); if you want to use
71 * chainloading or want to compile a u-boot binary that can be loaded into
72 * RAM via BDM set
Wolfgang Denka1be4762008-05-20 16:00:29 +020073 * "#if 0" to "#if 1"
wdenkc4cbd342005-01-09 18:21:42 +000074 * You will need a first stage bootloader then, e. g. colilo or a working BDM
75 * cable (Background Debug Mode)
76 *
77 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
78 *
Wolfgang Denk0708bc62010-10-07 21:51:12 +020079 * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
wdenkc4cbd342005-01-09 18:21:42 +000080 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
81 *
82 * ---
83 */
84
85#if 0
86#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
87#endif
88
89/* ---
90 * Configuration for environment
91 * Environment is embedded in u-boot in the second sector of the flash
92 * ---
93 */
94
angelo@sysam.it6312a952015-03-29 22:54:16 +020095#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060096 . = DEFINED(env_offset) ? env_offset : .; \
97 env/embedded.o(.text);
Jon Loeliger37ec35e2007-07-04 22:31:56 -050098
99/*
Jon Loeligere54e77a2007-07-10 09:29:01 -0500100 * BOOTP options
101 */
102#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeligere54e77a2007-07-10 09:29:01 -0500103
Jon Loeligere54e77a2007-07-10 09:29:01 -0500104/*
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500105 * Command line configuration.
wdenkc4cbd342005-01-09 18:21:42 +0000106 */
wdenkc4cbd342005-01-09 18:21:42 +0000107
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500108#ifdef CONFIG_MCFFEC
TsiChung Liewb3162452008-03-30 01:22:13 -0500109# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200110# define CONFIG_SYS_DISCOVER_PHY
111# define CONFIG_SYS_RX_ETH_BUFFER 8
112# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500113
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114# define CONFIG_SYS_FEC0_PINMUX 0
115# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denka1be4762008-05-20 16:00:29 +0200116# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
118# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500119# define FECDUPLEX FULL
120# define FECSPEED _100BASET
121# else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
123# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500124# endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500126#endif
wdenkc4cbd342005-01-09 18:21:42 +0000127
128/*
129 *-----------------------------------------------------------------------------
130 * Define user parameters that have to be customized most likely
131 *-----------------------------------------------------------------------------
132 */
133
134/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
135
wdenkc4cbd342005-01-09 18:21:42 +0000136/* The following settings will be contained in the environment block ; if you
137want to use a neutral environment all those settings can be manually set in
138u-boot: 'set' command */
139
140#if 0
141
142#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please
143enter a valid image address in flash */
144
wdenkc4cbd342005-01-09 18:21:42 +0000145/* User network settings */
146
wdenkc4cbd342005-01-09 18:21:42 +0000147#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
148#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
149
150#endif
151
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address
wdenkc4cbd342005-01-09 18:21:42 +0000153from which user programs will be started */
154
155/*---*/
156
wdenkc4cbd342005-01-09 18:21:42 +0000157/*
158 *-----------------------------------------------------------------------------
159 * End of user parameters to be customized
160 *-----------------------------------------------------------------------------
161 */
162
163/* ---
164 * Defines memory range for test
165 * ---
166 */
167
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168#define CONFIG_SYS_MEMTEST_START 0x400
169#define CONFIG_SYS_MEMTEST_END 0x380000
wdenkc4cbd342005-01-09 18:21:42 +0000170
171/* ---
172 * Low Level Configuration Settings
173 * (address mappings, register initial values, etc.)
174 * You should know what you are doing if you make changes here.
175 * ---
176 */
177
178/* ---
179 * Base register address
180 * ---
181 */
182
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
wdenkc4cbd342005-01-09 18:21:42 +0000184
185/* ---
186 * System Conf. Reg. & System Protection Reg.
187 * ---
188 */
189
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_SCR 0x0003
191#define CONFIG_SYS_SPR 0xffff
wdenkc4cbd342005-01-09 18:21:42 +0000192
193/* ---
194 * Ethernet settings
195 * ---
196 */
197
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_DISCOVER_PHY
199#define CONFIG_SYS_ENET_BD_BASE 0x780000
wdenkc4cbd342005-01-09 18:21:42 +0000200
201/*-----------------------------------------------------------------------
202 * Definitions for initial stack pointer and data area (in internal SRAM)
203 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200205#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200206#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc4cbd342005-01-09 18:21:42 +0000208
209/*-----------------------------------------------------------------------
210 * Start addresses for the final memory configuration
211 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc4cbd342005-01-09 18:21:42 +0000213 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenkc4cbd342005-01-09 18:21:42 +0000215
216/*
217 *-------------------------------------------------------------------------
218 * RAM SIZE (is defined above)
219 *-----------------------------------------------------------------------
220 */
221
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222/* #define CONFIG_SYS_SDRAM_SIZE 16 */
wdenkc4cbd342005-01-09 18:21:42 +0000223
224/*
225 *-----------------------------------------------------------------------
226 */
227
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenkc4cbd342005-01-09 18:21:42 +0000229
230#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200231#define CONFIG_SYS_MONITOR_BASE 0x20000
wdenkc4cbd342005-01-09 18:21:42 +0000232#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200233#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
wdenkc4cbd342005-01-09 18:21:42 +0000234#endif
235
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#define CONFIG_SYS_MONITOR_LEN 0x20000
237#define CONFIG_SYS_MALLOC_LEN (256 << 10)
238#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenkc4cbd342005-01-09 18:21:42 +0000239
240/*
241 * For booting Linux, the board info and command line data
242 * have to be in the first 8 MB of memory, since this is
243 * the maximum mapped by the Linux kernel during initialization ??
244 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200245#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc4cbd342005-01-09 18:21:42 +0000246
247/*-----------------------------------------------------------------------
248 * FLASH organization
249 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200250#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
251#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
252#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */
wdenkc4cbd342005-01-09 18:21:42 +0000253
254/*-----------------------------------------------------------------------
255 * Cache Configuration
256 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200257#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkc4cbd342005-01-09 18:21:42 +0000258
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600259#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200260 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600261#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200262 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600263#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
264#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
265 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
266 CF_ACR_EN | CF_ACR_SM_ALL)
267#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
268 CF_CACR_DISD | CF_CACR_INVI | \
269 CF_CACR_CEIB | CF_CACR_DCM | \
270 CF_CACR_EUSP)
271
wdenkc4cbd342005-01-09 18:21:42 +0000272/*-----------------------------------------------------------------------
273 * Memory bank definitions
274 *
275 * Please refer also to Motorola Coldfire user manual - Chapter XXX
276 * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
277 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200278#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
279#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
wdenkc4cbd342005-01-09 18:21:42 +0000280
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200281#define CONFIG_SYS_BR1_PRELIM 0
282#define CONFIG_SYS_OR1_PRELIM 0
wdenkc4cbd342005-01-09 18:21:42 +0000283
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200284#define CONFIG_SYS_BR2_PRELIM 0
285#define CONFIG_SYS_OR2_PRELIM 0
wdenkc4cbd342005-01-09 18:21:42 +0000286
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200287#define CONFIG_SYS_BR3_PRELIM 0
288#define CONFIG_SYS_OR3_PRELIM 0
wdenkc4cbd342005-01-09 18:21:42 +0000289
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200290#define CONFIG_SYS_BR4_PRELIM 0
291#define CONFIG_SYS_OR4_PRELIM 0
wdenkc4cbd342005-01-09 18:21:42 +0000292
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200293#define CONFIG_SYS_BR5_PRELIM 0
294#define CONFIG_SYS_OR5_PRELIM 0
wdenkc4cbd342005-01-09 18:21:42 +0000295
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200296#define CONFIG_SYS_BR6_PRELIM 0
297#define CONFIG_SYS_OR6_PRELIM 0
wdenkc4cbd342005-01-09 18:21:42 +0000298
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200299#define CONFIG_SYS_BR7_PRELIM 0x00000701
300#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
wdenkc4cbd342005-01-09 18:21:42 +0000301
302/*-----------------------------------------------------------------------
303 * LED config
304 */
305#define LED_STAT_0 0xffff /*all LEDs off*/
306#define LED_STAT_1 0xfffe
307#define LED_STAT_2 0xfffd
308#define LED_STAT_3 0xfffb
309#define LED_STAT_4 0xfff7
310#define LED_STAT_5 0xffef
311#define LED_STAT_6 0xffdf
312#define LED_STAT_7 0xff00 /*all LEDs on*/
313
314/*-----------------------------------------------------------------------
315 * Port configuration (GPIO)
316 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200317#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
wdenkc4cbd342005-01-09 18:21:42 +0000318GPIO*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200319#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
wdenkc4cbd342005-01-09 18:21:42 +0000320(1^=output, 0^=input) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200321#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
322#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
wdenkc4cbd342005-01-09 18:21:42 +0000323configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200324#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
325#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
326#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
wdenkc4cbd342005-01-09 18:21:42 +0000327
328#endif /* _CONFIG_COBRA5272_H */