blob: d11eb2dc6385092b12767cb7ef08a6538de76d6f [file] [log] [blame]
Andre Przywarae776fd22013-09-19 18:06:40 +02001/*
2 * code for switching cores into non-secure state
3 *
4 * Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26
27/* the vector table for secure state */
28_monitor_vectors:
29 .word 0 /* reset */
30 .word 0 /* undef */
31 adr pc, _secure_monitor
32 .word 0
33 .word 0
34 .word 0
35 .word 0
36 .word 0
37
38/*
39 * secure monitor handler
40 * U-boot calls this "software interrupt" in start.S
41 * This is executed on a "smc" instruction, we use a "smc #0" to switch
42 * to non-secure state.
43 * We use only r0 and r1 here, due to constraints in the caller.
44 */
45 .align 5
46_secure_monitor:
47 mrc p15, 0, r1, c1, c1, 0 @ read SCR
48 bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits
49 orr r1, r1, #0x31 @ enable NS, AW, FW bits
50
51 mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
52
53 movs pc, lr @ return to non-secure SVC