blob: 87e5fd54d9a801c55bdd5a4edf177589544c589e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Philippe CORNUdcbad9a2017-08-03 12:36:08 +02002/*
yannick fertre3e6077c2018-03-02 15:59:22 +01003 * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
4 * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
5 * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
Philippe CORNUdcbad9a2017-08-03 12:36:08 +02006 */
7
Patrick Delaunayb517c8f2020-11-06 19:01:57 +01008#define LOG_CATEGORY UCLASS_VIDEO
9
Philippe CORNUdcbad9a2017-08-03 12:36:08 +020010#include <common.h>
11#include <clk.h>
Yannick Fertréd6117082019-10-07 15:29:02 +020012#include <display.h>
Philippe CORNUdcbad9a2017-08-03 12:36:08 +020013#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060014#include <log.h>
Philippe CORNUdcbad9a2017-08-03 12:36:08 +020015#include <panel.h>
yannick fertre28dc09b2018-03-02 15:59:21 +010016#include <reset.h>
Philippe CORNUdcbad9a2017-08-03 12:36:08 +020017#include <video.h>
Yannick Fertréd6117082019-10-07 15:29:02 +020018#include <video_bridge.h>
Philippe CORNUdcbad9a2017-08-03 12:36:08 +020019#include <asm/io.h>
Philippe CORNUdcbad9a2017-08-03 12:36:08 +020020#include <dm/device-internal.h>
Simon Glass9bc15642020-02-03 07:36:16 -070021#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060022#include <linux/bitops.h>
Philippe CORNUdcbad9a2017-08-03 12:36:08 +020023
Philippe CORNUdcbad9a2017-08-03 12:36:08 +020024struct stm32_ltdc_priv {
25 void __iomem *regs;
Philippe CORNUdcbad9a2017-08-03 12:36:08 +020026 enum video_log2_bpp l2bpp;
27 u32 bg_col_argb;
28 u32 crop_x, crop_y, crop_w, crop_h;
29 u32 alpha;
30};
31
32/* LTDC main registers */
33#define LTDC_IDR 0x00 /* IDentification */
34#define LTDC_LCR 0x04 /* Layer Count */
35#define LTDC_SSCR 0x08 /* Synchronization Size Configuration */
36#define LTDC_BPCR 0x0C /* Back Porch Configuration */
37#define LTDC_AWCR 0x10 /* Active Width Configuration */
38#define LTDC_TWCR 0x14 /* Total Width Configuration */
39#define LTDC_GCR 0x18 /* Global Control */
40#define LTDC_GC1R 0x1C /* Global Configuration 1 */
41#define LTDC_GC2R 0x20 /* Global Configuration 2 */
42#define LTDC_SRCR 0x24 /* Shadow Reload Configuration */
43#define LTDC_GACR 0x28 /* GAmma Correction */
44#define LTDC_BCCR 0x2C /* Background Color Configuration */
45#define LTDC_IER 0x34 /* Interrupt Enable */
46#define LTDC_ISR 0x38 /* Interrupt Status */
47#define LTDC_ICR 0x3C /* Interrupt Clear */
48#define LTDC_LIPCR 0x40 /* Line Interrupt Position Conf. */
49#define LTDC_CPSR 0x44 /* Current Position Status */
50#define LTDC_CDSR 0x48 /* Current Display Status */
51
52/* LTDC layer 1 registers */
53#define LTDC_L1LC1R 0x80 /* L1 Layer Configuration 1 */
54#define LTDC_L1LC2R 0x84 /* L1 Layer Configuration 2 */
55#define LTDC_L1CR 0x84 /* L1 Control */
56#define LTDC_L1WHPCR 0x88 /* L1 Window Hor Position Config */
57#define LTDC_L1WVPCR 0x8C /* L1 Window Vert Position Config */
58#define LTDC_L1CKCR 0x90 /* L1 Color Keying Configuration */
59#define LTDC_L1PFCR 0x94 /* L1 Pixel Format Configuration */
60#define LTDC_L1CACR 0x98 /* L1 Constant Alpha Config */
61#define LTDC_L1DCCR 0x9C /* L1 Default Color Configuration */
62#define LTDC_L1BFCR 0xA0 /* L1 Blend Factors Configuration */
63#define LTDC_L1FBBCR 0xA4 /* L1 FrameBuffer Bus Control */
64#define LTDC_L1AFBCR 0xA8 /* L1 AuxFB Control */
65#define LTDC_L1CFBAR 0xAC /* L1 Color FrameBuffer Address */
66#define LTDC_L1CFBLR 0xB0 /* L1 Color FrameBuffer Length */
67#define LTDC_L1CFBLNR 0xB4 /* L1 Color FrameBuffer Line Nb */
68#define LTDC_L1AFBAR 0xB8 /* L1 AuxFB Address */
69#define LTDC_L1AFBLR 0xBC /* L1 AuxFB Length */
70#define LTDC_L1AFBLNR 0xC0 /* L1 AuxFB Line Number */
71#define LTDC_L1CLUTWR 0xC4 /* L1 CLUT Write */
72
73/* Bit definitions */
74#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
75#define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
76
77#define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
78#define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
79
80#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
81#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
82
83#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
84#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
85
86#define GCR_LTDCEN BIT(0) /* LTDC ENable */
87#define GCR_DEN BIT(16) /* Dither ENable */
88#define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
89#define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
90#define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
91#define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
92
93#define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
94#define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
95#define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
96#define GC1R_PBEN BIT(12) /* Precise Blending ENable */
97#define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
98#define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
99#define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
100#define GC1R_BCP BIT(22) /* Background Colour Programmable */
101#define GC1R_BBEN BIT(23) /* Background Blending ENabled */
102#define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
103#define GC1R_TP BIT(25) /* Timing Programmable */
104#define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
105#define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
106#define GC1R_DWP BIT(28) /* Dither Width Programmable */
107#define GC1R_STREN BIT(29) /* STatus Registers ENabled */
108#define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
109
110#define GC2R_EDCA BIT(0) /* External Display Control Ability */
111#define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
112#define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
113#define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
114#define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
115#define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
116
117#define SRCR_IMR BIT(0) /* IMmediate Reload */
118#define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
119
120#define LXCR_LEN BIT(0) /* Layer ENable */
121#define LXCR_COLKEN BIT(1) /* Color Keying Enable */
122#define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
123
124#define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
125#define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
126
127#define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
128#define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
129
130#define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
131
132#define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
133
134#define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
135#define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
136
137#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
138#define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
139
140#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
141
142#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
yannick fertre8fa461e2018-03-02 15:59:25 +0100143#define BF1_CA 0x400 /* Constant Alpha */
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200144#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
yannick fertre8fa461e2018-03-02 15:59:25 +0100145#define BF2_1CA 0x005 /* 1 - Constant Alpha */
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200146
147enum stm32_ltdc_pix_fmt {
148 PF_ARGB8888 = 0,
149 PF_RGB888,
150 PF_RGB565,
151 PF_ARGB1555,
152 PF_ARGB4444,
153 PF_L8,
154 PF_AL44,
155 PF_AL88
156};
157
158/* TODO add more color format support */
159static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
160{
161 enum stm32_ltdc_pix_fmt pf;
162
163 switch (l2bpp) {
164 case VIDEO_BPP16:
165 pf = PF_RGB565;
166 break;
167
yannick fertre8fa461e2018-03-02 15:59:25 +0100168 case VIDEO_BPP32:
169 pf = PF_ARGB8888;
170 break;
171
172 case VIDEO_BPP8:
173 pf = PF_L8;
174 break;
175
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200176 case VIDEO_BPP1:
177 case VIDEO_BPP2:
178 case VIDEO_BPP4:
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200179 default:
Patrick Delaunayb517c8f2020-11-06 19:01:57 +0100180 log_warning("warning %dbpp not supported yet, %dbpp instead\n",
181 VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200182 pf = PF_RGB565;
183 break;
184 }
185
Patrick Delaunayb517c8f2020-11-06 19:01:57 +0100186 log_debug("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200187
188 return (u32)pf;
189}
190
yannick fertre8fa461e2018-03-02 15:59:25 +0100191static bool has_alpha(u32 fmt)
192{
193 switch (fmt) {
194 case PF_ARGB8888:
195 case PF_ARGB1555:
196 case PF_ARGB4444:
197 case PF_AL44:
198 case PF_AL88:
199 return true;
200 case PF_RGB888:
201 case PF_RGB565:
202 case PF_L8:
203 default:
204 return false;
205 }
206}
207
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200208static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
209{
210 /* Reload configuration immediately & enable LTDC */
211 setbits_le32(priv->regs + LTDC_SRCR, SRCR_IMR);
212 setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
213}
214
Yannick Fertréd6117082019-10-07 15:29:02 +0200215static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
216 struct display_timing *timings)
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200217{
218 void __iomem *regs = priv->regs;
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200219 u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
220 u32 total_w, total_h;
221 u32 val;
222
223 /* Convert video timings to ltdc timings */
Yannick Fertréd6117082019-10-07 15:29:02 +0200224 hsync = timings->hsync_len.typ - 1;
225 vsync = timings->vsync_len.typ - 1;
226 acc_hbp = hsync + timings->hback_porch.typ;
227 acc_vbp = vsync + timings->vback_porch.typ;
228 acc_act_w = acc_hbp + timings->hactive.typ;
229 acc_act_h = acc_vbp + timings->vactive.typ;
230 total_w = acc_act_w + timings->hfront_porch.typ;
231 total_h = acc_act_h + timings->vfront_porch.typ;
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200232
233 /* Synchronization sizes */
234 val = (hsync << 16) | vsync;
235 clrsetbits_le32(regs + LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
236
237 /* Accumulated back porch */
238 val = (acc_hbp << 16) | acc_vbp;
239 clrsetbits_le32(regs + LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
240
241 /* Accumulated active width */
242 val = (acc_act_w << 16) | acc_act_h;
243 clrsetbits_le32(regs + LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
244
245 /* Total width & height */
246 val = (total_w << 16) | total_h;
247 clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
248
yannick fertred0cfebf2018-03-02 15:59:24 +0100249 setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
250
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200251 /* Signal polarities */
252 val = 0;
Patrick Delaunayb517c8f2020-11-06 19:01:57 +0100253 log_debug("timing->flags 0x%08x\n", timings->flags);
Yannick Fertréd6117082019-10-07 15:29:02 +0200254 if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200255 val |= GCR_HSPOL;
Yannick Fertréd6117082019-10-07 15:29:02 +0200256 if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200257 val |= GCR_VSPOL;
Yannick Fertréd6117082019-10-07 15:29:02 +0200258 if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200259 val |= GCR_DEPOL;
Yannick Fertréd6117082019-10-07 15:29:02 +0200260 if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200261 val |= GCR_PCPOL;
262 clrsetbits_le32(regs + LTDC_GCR,
263 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
264
265 /* Overall background color */
266 writel(priv->bg_col_argb, priv->regs + LTDC_BCCR);
267}
268
269static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
270{
271 void __iomem *regs = priv->regs;
272 u32 x0, x1, y0, y1;
273 u32 pitch_in_bytes;
274 u32 line_length;
275 u32 bus_width;
276 u32 val, tmp, bpp;
yannick fertre8fa461e2018-03-02 15:59:25 +0100277 u32 format;
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200278
279 x0 = priv->crop_x;
280 x1 = priv->crop_x + priv->crop_w - 1;
281 y0 = priv->crop_y;
282 y1 = priv->crop_y + priv->crop_h - 1;
283
284 /* Horizontal start and stop position */
285 tmp = (readl(regs + LTDC_BPCR) & BPCR_AHBP) >> 16;
286 val = ((x1 + 1 + tmp) << 16) + (x0 + 1 + tmp);
287 clrsetbits_le32(regs + LTDC_L1WHPCR, LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS,
288 val);
289
290 /* Vertical start & stop position */
291 tmp = readl(regs + LTDC_BPCR) & BPCR_AVBP;
292 val = ((y1 + 1 + tmp) << 16) + (y0 + 1 + tmp);
293 clrsetbits_le32(regs + LTDC_L1WVPCR, LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS,
294 val);
295
296 /* Layer background color */
297 writel(priv->bg_col_argb, regs + LTDC_L1DCCR);
298
299 /* Color frame buffer pitch in bytes & line length */
300 bpp = VNBITS(priv->l2bpp);
301 pitch_in_bytes = priv->crop_w * (bpp >> 3);
302 bus_width = 8 << ((readl(regs + LTDC_GC2R) & GC2R_BW) >> 4);
303 line_length = ((bpp >> 3) * priv->crop_w) + (bus_width >> 3) - 1;
304 val = (pitch_in_bytes << 16) | line_length;
305 clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
306
307 /* Pixel format */
yannick fertre8fa461e2018-03-02 15:59:25 +0100308 format = stm32_ltdc_get_pixel_format(priv->l2bpp);
309 clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format);
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200310
311 /* Constant alpha value */
312 clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
313
yannick fertre8fa461e2018-03-02 15:59:25 +0100314 /* Specifies the blending factors : with or without pixel alpha */
315 /* Manage hw-specific capabilities */
316 val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
317
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200318 /* Blending factors */
yannick fertre8fa461e2018-03-02 15:59:25 +0100319 clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200320
321 /* Frame buffer line number */
322 clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
323
324 /* Frame buffer address */
325 writel(fb_addr, regs + LTDC_L1CFBAR);
326
327 /* Enable layer 1 */
328 setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
329}
330
331static int stm32_ltdc_probe(struct udevice *dev)
332{
Simon Glassb75b15b2020-12-03 16:55:23 -0700333 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200334 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
335 struct stm32_ltdc_priv *priv = dev_get_priv(dev);
Yannick Fertréd6117082019-10-07 15:29:02 +0200336 struct udevice *bridge = NULL;
337 struct udevice *panel = NULL;
338 struct display_timing timings;
yannick fertre8d6237b2018-03-02 15:59:23 +0100339 struct clk pclk;
yannick fertre28dc09b2018-03-02 15:59:21 +0100340 struct reset_ctl rst;
Yannick Fertréd6117082019-10-07 15:29:02 +0200341 int ret;
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200342
343 priv->regs = (void *)dev_read_addr(dev);
344 if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
Yannick Fertréd6117082019-10-07 15:29:02 +0200345 dev_err(dev, "ltdc dt register address error\n");
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200346 return -EINVAL;
347 }
348
yannick fertre8d6237b2018-03-02 15:59:23 +0100349 ret = clk_get_by_index(dev, 0, &pclk);
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200350 if (ret) {
Yannick Fertréd6117082019-10-07 15:29:02 +0200351 dev_err(dev, "peripheral clock get error %d\n", ret);
yannick fertre8d6237b2018-03-02 15:59:23 +0100352 return ret;
353 }
354
355 ret = clk_enable(&pclk);
356 if (ret) {
Yannick Fertréd6117082019-10-07 15:29:02 +0200357 dev_err(dev, "peripheral clock enable error %d\n", ret);
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200358 return ret;
359 }
360
Yannick Fertréd6117082019-10-07 15:29:02 +0200361 ret = uclass_first_device_err(UCLASS_PANEL, &panel);
yannick fertre28dc09b2018-03-02 15:59:21 +0100362 if (ret) {
Yannick Fertréd6117082019-10-07 15:29:02 +0200363 if (ret != -ENODEV)
364 dev_err(dev, "panel device error %d\n", ret);
365 return ret;
yannick fertre28dc09b2018-03-02 15:59:21 +0100366 }
367
Yannick Fertréd6117082019-10-07 15:29:02 +0200368 ret = panel_get_display_timing(panel, &timings);
yannick fertre8d6237b2018-03-02 15:59:23 +0100369 if (ret) {
Patrick Delaunay1d646412020-09-09 17:44:12 +0200370 ret = ofnode_decode_display_timing(dev_ofnode(panel),
Yannick Fertréd6117082019-10-07 15:29:02 +0200371 0, &timings);
372 if (ret) {
373 dev_err(dev, "decode display timing error %d\n", ret);
374 return ret;
375 }
yannick fertre8d6237b2018-03-02 15:59:23 +0100376 }
377
Yannick Fertréd6117082019-10-07 15:29:02 +0200378 ret = clk_set_rate(&pclk, timings.pixelclock.typ);
379 if (ret)
380 dev_warn(dev, "fail to set pixel clock %d hz\n",
381 timings.pixelclock.typ);
382
Patrick Delaunayb517c8f2020-11-06 19:01:57 +0100383 dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
384 timings.pixelclock.typ, clk_get_rate(&pclk));
Yannick Fertréd6117082019-10-07 15:29:02 +0200385
386 ret = reset_get_by_index(dev, 0, &rst);
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200387 if (ret) {
Yannick Fertréd6117082019-10-07 15:29:02 +0200388 dev_err(dev, "missing ltdc hardware reset\n");
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200389 return ret;
390 }
391
Yannick Fertréd6117082019-10-07 15:29:02 +0200392 /* Reset */
393 reset_deassert(&rst);
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200394
Yannick Fertréd6117082019-10-07 15:29:02 +0200395 if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
396 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
397 if (ret)
Patrick Delaunayb517c8f2020-11-06 19:01:57 +0100398 dev_dbg(dev,
399 "No video bridge, or no backlight on bridge\n");
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200400
Yannick Fertréd6117082019-10-07 15:29:02 +0200401 if (bridge) {
402 ret = video_bridge_attach(bridge);
403 if (ret) {
Patrick Delaunayb517c8f2020-11-06 19:01:57 +0100404 dev_err(bridge, "fail to attach bridge\n");
Yannick Fertréd6117082019-10-07 15:29:02 +0200405 return ret;
406 }
407 }
408 }
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200409
410 /* TODO Below parameters are hard-coded for the moment... */
411 priv->l2bpp = VIDEO_BPP16;
412 priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
413 priv->crop_x = 0;
414 priv->crop_y = 0;
Yannick Fertréd6117082019-10-07 15:29:02 +0200415 priv->crop_w = timings.hactive.typ;
416 priv->crop_h = timings.vactive.typ;
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200417 priv->alpha = 0xFF;
418
Patrick Delaunayb517c8f2020-11-06 19:01:57 +0100419 dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n",
420 timings.hactive.typ, timings.vactive.typ,
421 VNBITS(priv->l2bpp), uc_plat->base);
422 dev_dbg(dev, "crop %d,%d %dx%d bg 0x%08x alpha %d\n",
423 priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
424 priv->bg_col_argb, priv->alpha);
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200425
426 /* Configure & start LTDC */
Yannick Fertréd6117082019-10-07 15:29:02 +0200427 stm32_ltdc_set_mode(priv, &timings);
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200428 stm32_ltdc_set_layer1(priv, uc_plat->base);
429 stm32_ltdc_enable(priv);
430
Yannick Fertréd6117082019-10-07 15:29:02 +0200431 uc_priv->xsize = timings.hactive.typ;
432 uc_priv->ysize = timings.vactive.typ;
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200433 uc_priv->bpix = priv->l2bpp;
434
Yannick Fertréd6117082019-10-07 15:29:02 +0200435 if (!bridge) {
436 ret = panel_enable_backlight(panel);
437 if (ret) {
438 dev_err(dev, "panel %s enable backlight error %d\n",
439 panel->name, ret);
440 return ret;
441 }
442 } else if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
443 ret = video_bridge_set_backlight(bridge, 80);
444 if (ret) {
445 dev_err(dev, "fail to set backlight\n");
446 return ret;
447 }
448 }
449
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200450 video_set_flush_dcache(dev, true);
451
452 return 0;
453}
454
455static int stm32_ltdc_bind(struct udevice *dev)
456{
Simon Glassb75b15b2020-12-03 16:55:23 -0700457 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200458
459 uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
460 CONFIG_VIDEO_STM32_MAX_YRES *
461 (CONFIG_VIDEO_STM32_MAX_BPP >> 3);
Patrick Delaunayb1a756b2021-11-15 16:32:22 +0100462 /* align framebuffer on kernel MMU_SECTION_SIZE = max 2MB for LPAE */
463 uc_plat->align = SZ_2M;
464 dev_dbg(dev, "frame buffer max size %d bytes align %x\n",
465 uc_plat->size, uc_plat->align);
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200466
467 return 0;
468}
469
470static const struct udevice_id stm32_ltdc_ids[] = {
471 { .compatible = "st,stm32-ltdc" },
472 { }
473};
474
475U_BOOT_DRIVER(stm32_ltdc) = {
yannick fertre3e6077c2018-03-02 15:59:22 +0100476 .name = "stm32_display",
477 .id = UCLASS_VIDEO,
478 .of_match = stm32_ltdc_ids,
479 .probe = stm32_ltdc_probe,
480 .bind = stm32_ltdc_bind,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700481 .priv_auto = sizeof(struct stm32_ltdc_priv),
Philippe CORNUdcbad9a2017-08-03 12:36:08 +0200482};