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git01.mediatek.com / filogic / uboot / e72dcd481b5dd89695773262e4938272b154d6e0 / . / drivers / ram / starfive / starfive_ddr.c
blob: 553f2ce6f441904346c83ad529dbc47b1bf01c30 [file] [log] [blame]
Yanhong Wangd60e8802023-03-29 11:42:16 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
5 */
6
7#include <common.h>
8#include <asm/arch/regs.h>
9#include <asm/io.h>
10#include <clk.h>
11#include <dm.h>
12#include <fdtdec.h>
13#include <init.h>
14#include <linux/bitops.h>
15#include <linux/sizes.h>
16#include <linux/delay.h>
17#include <ram.h>
18#include <reset.h>
19
20#include "starfive_ddr.h"
21
22DECLARE_GLOBAL_DATA_PTR;
23
24struct starfive_ddr_priv {
25 struct udevice *dev;
26 struct ram_info info;
27 void __iomem *ctrlreg;
28 void __iomem *phyreg;
29 struct reset_ctl_bulk rst;
30 struct clk clk;
31 u32 fre;
32};
33
34static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *priv)
35{
36 enum ddr_size_t size;
37
38 switch (priv->info.size) {
39 case SZ_2G:
40 size = DDR_SIZE_2G;
41 break;
42
43 case SZ_4G:
44 size = DDR_SIZE_4G;
45 break;
46
47 case 0x200000000:
48 size = DDR_SIZE_8G;
49 break;
50
51 case 0x400000000:
52 default:
53 pr_err("unsupport size %lx\n", priv->info.size);
54 return -EINVAL;
55 }
56
57 ddr_phy_train(priv->phyreg + (PHY_BASE_ADDR << 2));
58 ddr_phy_util(priv->phyreg + (PHY_AC_BASE_ADDR << 2));
59 ddr_phy_start(priv->phyreg, size);
60
61 DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
62 ddrcsr_boot(priv->ctrlreg, priv->ctrlreg + SEC_CTRL_ADDR,
63 priv->phyreg, size);
64
65 return 0;
66}
67
68static int starfive_ddr_probe(struct udevice *dev)
69{
70 struct starfive_ddr_priv *priv = dev_get_priv(dev);
71 fdt_addr_t addr;
72 u64 rate;
73 int ret;
74
75 /* Read memory base and size from DT */
76 fdtdec_setup_mem_size_base();
77 priv->info.base = gd->ram_base;
78 priv->info.size = gd->ram_size;
79
80 priv->dev = dev;
81 addr = dev_read_addr_index(dev, 0);
82 if (addr == FDT_ADDR_T_NONE)
83 return -EINVAL;
84
85 priv->ctrlreg = (void __iomem *)addr;
86 addr = dev_read_addr_index(dev, 1);
87 if (addr == FDT_ADDR_T_NONE)
88 return -EINVAL;
89
90 priv->phyreg = (void __iomem *)addr;
91 ret = dev_read_u32(dev, "clock-frequency", &priv->fre);
92 if (ret)
93 return ret;
94
95 switch (priv->fre) {
96 case 2133:
97 rate = 1066000000;
98 break;
99
100 case 2800:
101 rate = 1400000000;
102 break;
103
104 default:
105 pr_err("Unknown DDR frequency %d\n", priv->fre);
106 return -EINVAL;
107 };
108
109 ret = reset_get_bulk(dev, &priv->rst);
110 if (ret)
111 return ret;
112
113 ret = reset_deassert_bulk(&priv->rst);
114 if (ret < 0)
115 return ret;
116
117 ret = clk_get_by_index(dev, 0, &priv->clk);
118 if (ret)
119 goto err_free_reset;
120
121 ret = clk_set_rate(&priv->clk, rate);
122 if (ret < 0)
123 goto err_free_reset;
124
125 ret = starfive_ddr_setup(dev, priv);
126 printf("DDR version: dc2e84f0.\n");
127
128 return ret;
129
130err_free_reset:
131 reset_release_bulk(&priv->rst);
132
133 return ret;
134}
135
136static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info)
137{
138 struct starfive_ddr_priv *priv = dev_get_priv(dev);
139
140 *info = priv->info;
141
142 return 0;
143}
144
145static struct ram_ops starfive_ddr_ops = {
146 .get_info = starfive_ddr_get_info,
147};
148
149static const struct udevice_id starfive_ddr_ids[] = {
150 { .compatible = "starfive,jh7110-dmc" },
151 { }
152};
153
154U_BOOT_DRIVER(starfive_ddr) = {
155 .name = "starfive_ddr",
156 .id = UCLASS_RAM,
157 .of_match = starfive_ddr_ids,
158 .ops = &starfive_ddr_ops,
159 .probe = starfive_ddr_probe,
160 .priv_auto = sizeof(struct starfive_ddr_priv),
161};