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Stefan Roesee1b8d0b2012-08-14 15:04:19 +02001/*
Stefan Roese9071a442013-04-25 23:20:23 +00002 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
Stefan Roesee1b8d0b2012-08-14 15:04:19 +02003 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesee1b8d0b2012-08-14 15:04:19 +02005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10/*
11 * High Level Configuration Options
12 * (easy to change)
13 */
14
15#define CONFIG_MPC5200
Masahiro Yamada608ed2c2014-01-16 11:03:07 +090016#define CONFIG_A3M071 /* A3M071 board */
Stefan Roesee1b8d0b2012-08-14 15:04:19 +020017
18#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
19
Stefan Roese512da3b2013-02-07 02:10:11 +000020#define CONFIG_SPL_TARGET "u-boot-img.bin"
21
Stefan Roesee1b8d0b2012-08-14 15:04:19 +020022#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
23
24#define CONFIG_MISC_INIT_R
25#define CONFIG_SYS_LOWBOOT /* Enable lowboot */
26
Stefan Roese512da3b2013-02-07 02:10:11 +000027#ifdef CONFIG_A4M2K
28#define CONFIG_HOSTNAME a4m2k
29#else
30#define CONFIG_HOSTNAME a3m071
31#endif
32
Stefan Roese5c1617b2013-06-22 16:16:25 +020033#define CONFIG_BOOTCOUNT_LIMIT
34
Stefan Roesee1b8d0b2012-08-14 15:04:19 +020035/*
36 * Serial console configuration
37 */
38#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
39#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
40#define CONFIG_SYS_BAUDRATE_TABLE \
41 { 9600, 19200, 38400, 57600, 115200, 230400 }
42
43/*
44 * Command line configuration.
45 */
Stefan Roesee1b8d0b2012-08-14 15:04:19 +020046#define CONFIG_CMD_BSP
Stefan Roesee1b8d0b2012-08-14 15:04:19 +020047#define CONFIG_CMD_REGINFO
Stefan Roese9071a442013-04-25 23:20:23 +000048#define CONFIG_BOOTP_SEND_HOSTNAME
49#define CONFIG_BOOTP_SERVERIP
50#define CONFIG_BOOTP_MAY_FAIL
51#define CONFIG_BOOTP_BOOTPATH
52#define CONFIG_BOOTP_GATEWAY
53#define CONFIG_BOOTP_SERVERIP
54#define CONFIG_NET_RETRY_COUNT 3
Stefan Roese9071a442013-04-25 23:20:23 +000055#define CONFIG_NETCONSOLE
56#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Stefan Roese9071a442013-04-25 23:20:23 +000057#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
58#define CONFIG_MTD_PARTITIONS /* needed for UBI */
59#define CONFIG_FLASH_CFI_MTD
60#define MTDIDS_DEFAULT "nor0=fc000000.flash"
61#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
Stefan Roese5c1617b2013-06-22 16:16:25 +020062 "128k(env1)," \
63 "128k(env2)," \
Stefan Roese9071a442013-04-25 23:20:23 +000064 "128k(hwinfo)," \
65 "1M(nvramsim)," \
66 "128k(dtb)," \
67 "5M(kernel)," \
68 "128k(sysinfo)," \
69 "7552k(root)," \
70 "4M(app)," \
Stefan Roese5c1617b2013-06-22 16:16:25 +020071 "5376k(data)," \
72 "8M(install)"
73
Stefan Roese9071a442013-04-25 23:20:23 +000074#define CONFIG_LZO /* needed for UBI */
75#define CONFIG_RBTREE /* needed for UBI */
76#define CONFIG_CMD_MTDPARTS
Stefan Roese9071a442013-04-25 23:20:23 +000077#define CONFIG_CMD_UBIFS
Stefan Roesee1b8d0b2012-08-14 15:04:19 +020078
79/*
80 * IPB Bus clocking configuration.
81 */
82#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
83/* define for 66MHz speed - undef for 33MHz PCI clock speed */
Stefan Roese512da3b2013-02-07 02:10:11 +000084#ifdef CONFIG_A4M2K
85#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
86#else
Stefan Roesee1b8d0b2012-08-14 15:04:19 +020087#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
Stefan Roese512da3b2013-02-07 02:10:11 +000088#endif
Stefan Roesee1b8d0b2012-08-14 15:04:19 +020089
Stefan Roesee1b8d0b2012-08-14 15:04:19 +020090/* maximum size of the flat tree (8K) */
91#define OF_FLAT_TREE_MAX_SIZE 8192
92
93#define OF_CPU "PowerPC,5200@0"
94#define OF_SOC "soc5200@f0000000"
95#define OF_TBCLK (bd->bi_busfreq / 4)
96#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
97
98/*
Stefan Roesee1b8d0b2012-08-14 15:04:19 +020099 * NOR flash configuration
100 */
101#define CONFIG_SYS_FLASH_BASE 0xfc000000
Stefan Roese512da3b2013-02-07 02:10:11 +0000102#define CONFIG_SYS_FLASH_SIZE 0x02000000
Stefan Roese9071a442013-04-25 23:20:23 +0000103#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200104
105#define CONFIG_SYS_MAX_FLASH_BANKS 1
106#define CONFIG_SYS_MAX_FLASH_SECT 256
107#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
108#define CONFIG_SYS_FLASH_WRITE_TOUT 500
109#define CONFIG_SYS_FLASH_LOCK_TOUT 5
110#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
111#define CONFIG_SYS_FLASH_PROTECTION
112#define CONFIG_FLASH_CFI_DRIVER
113#define CONFIG_SYS_FLASH_CFI
114#define CONFIG_SYS_FLASH_EMPTY_INFO
115#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Stefan Roeseeba076f2013-04-04 03:55:42 +0000116#define CONFIG_FLASH_VERIFY
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200117
118/*
119 * Environment settings
120 */
121#define CONFIG_ENV_IS_IN_FLASH
122#define CONFIG_ENV_SIZE 0x10000
123#define CONFIG_ENV_SECT_SIZE 0x20000
124#define CONFIG_ENV_OVERWRITE
Stefan Roese9071a442013-04-25 23:20:23 +0000125#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
126#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200127
128/*
129 * Memory map
130 */
131#define CONFIG_SYS_MBAR 0xf0000000
132#define CONFIG_SYS_SDRAM_BASE 0x00000000
133#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
134
135/* Use SRAM until RAM will be available */
136#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
York Sun515fbb42016-04-06 13:22:10 -0700137#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200138
York Sun515fbb42016-04-06 13:22:10 -0700139#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Stefan Roese1c419762013-04-25 23:10:02 +0000140 GENERATED_GBL_DATA_SIZE)
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200141#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
142
143#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
144
Stefan Roese9071a442013-04-25 23:20:23 +0000145#define CONFIG_SYS_MONITOR_LEN (512 << 10)
146#define CONFIG_SYS_MALLOC_LEN (4 << 20)
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200147#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
148
149/*
150 * Ethernet configuration
151 */
152#define CONFIG_MPC5xxx_FEC
153#define CONFIG_MPC5xxx_FEC_MII100
Stefan Roese512da3b2013-02-07 02:10:11 +0000154#ifdef CONFIG_A4M2K
155#define CONFIG_PHY_ADDR 0x01
156#else
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200157#define CONFIG_PHY_ADDR 0x00
Stefan Roese512da3b2013-02-07 02:10:11 +0000158#endif
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200159
160/*
161 * GPIO configuration
162 */
163
164/*
165 * GPIO-config depends on failsave-level
166 * failsave 0 means just MPX-config, no digiboard, no fpga
167 * 1 means digiboard ok
168 * 2 means fpga ok
169 */
170
Stefan Roese512da3b2013-02-07 02:10:11 +0000171#ifdef CONFIG_A4M2K
Stefan Roese9071a442013-04-25 23:20:23 +0000172#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
Stefan Roese512da3b2013-02-07 02:10:11 +0000173#else
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200174/* for failsave-level 0 - full failsave */
175#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
176/* for failsave-level 1 - only digiboard ok */
Stefan Roese9071a442013-04-25 23:20:23 +0000177#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200178/* for failsave-level 2 - all ok */
Stefan Roese9071a442013-04-25 23:20:23 +0000179#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
Stefan Roese512da3b2013-02-07 02:10:11 +0000180#endif
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200181
Stefan Roese223008d2013-02-07 02:10:28 +0000182#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
183#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
184#define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
185#endif
186
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200187/*
188 * Configuration matrix
Stefan Roese9071a442013-04-25 23:20:23 +0000189 * MSB LSB
Stefan Roese512da3b2013-02-07 02:10:11 +0000190 * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
Stefan Roese9071a442013-04-25 23:20:23 +0000191 * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
192 * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200193 * || ||| || | ||| | | | |
194 * || ||| || | ||| | | | | bit rev name
195 * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
196 * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
197 * ||| || | ||| | | | | 2 29 ALTs
198 * +++-++--+---+++-+---+---+---+- 3 28 ALTs
199 * ++-++--+---+++-+---+---+---+- 4 27 CS7
200 * +-++--+---+++-+---+---+---+- 5 26 CS6
201 * || | ||| | | | | 6 25 ATA
202 * ++--+---+++-+---+---+---+- 7 24 ATA
203 * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
204 * | ||| | | | | 9 22 IRDA
205 * | ||| | | | | 10 21 IRDA
206 * +---+++-+---+---+---+- 11 20 IRDA
207 * ||| | | | | 12 19 Ether
208 * ||| | | | | 13 18 Ether
209 * ||| | | | | 14 17 Ether
210 * +++-+---+---+---+- 15 16 Ether
211 * ++-+---+---+---+- 16 15 PCI_DIS
212 * +-+---+---+---+- 17 14 USB_SE
213 * | | | | 18 13 USB
214 * +---+---+---+- 19 12 USB
215 * | | | 20 11 PSC3
216 * | | | 21 10 PSC3
217 * | | | 22 9 PSC3
218 * +---+---+- 23 8 PSC3
219 * | | 24 7 -
220 * | | 25 6 PSC2
221 * | | 26 5 PSC2
222 * +---+- 27 4 PSC2
223 * | 28 3 -
224 * | 29 2 PSC1
225 * | 30 1 PSC1
226 * +- 31 0 PSC1
227 */
228
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200229/*
230 * Miscellaneous configurable options
231 */
232#define CONFIG_SYS_LONGHELP
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200233
234#define CONFIG_CMDLINE_EDITING
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200235
236#if defined(CONFIG_CMD_KGDB)
237#define CONFIG_SYS_CBSIZE 1024
238#else
239#define CONFIG_SYS_CBSIZE 256
240#endif
241#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
242#define CONFIG_SYS_MAXARGS 16
243#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
244
245#define CONFIG_SYS_MEMTEST_START 0x00100000
246#define CONFIG_SYS_MEMTEST_END 0x00f00000
247
248#define CONFIG_SYS_LOAD_ADDR 0x00100000
249
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200250#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
251
252/*
253 * Various low-level settings
254 */
255#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
256#define CONFIG_SYS_HID0_FINAL HID0_ICE
257
258#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
259#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
260#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
261#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Stefan Roese512da3b2013-02-07 02:10:11 +0000262
263#ifdef CONFIG_A4M2K
264/* external MRAM */
265#define CONFIG_SYS_CS1_START 0xf1000000
266#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
267#endif
268
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200269#define CONFIG_SYS_CS2_START 0xe0000000
270#define CONFIG_SYS_CS2_SIZE 0x00100000
271
Stefan Roese512da3b2013-02-07 02:10:11 +0000272/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200273#define CONFIG_SYS_CS3_START 0xE9000000
Stefan Roese512da3b2013-02-07 02:10:11 +0000274#ifdef CONFIG_A4M2K
275#define CONFIG_SYS_CS3_SIZE 0x00100000
276#else
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200277#define CONFIG_SYS_CS3_SIZE 0x00080000
Stefan Roese512da3b2013-02-07 02:10:11 +0000278#endif
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200279/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
280#define CONFIG_SYS_CS3_CFG 0x0032B900
281
Stefan Roese512da3b2013-02-07 02:10:11 +0000282#ifndef CONFIG_A4M2K
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200283/* Diagnosis Interface - see ticket #63 */
284#define CONFIG_SYS_CS4_START 0xEA000000
285#define CONFIG_SYS_CS4_SIZE 0x00000001
286/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
287#define CONFIG_SYS_CS4_CFG 0x0002B900
Stefan Roese512da3b2013-02-07 02:10:11 +0000288#endif
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200289
Stefan Roese512da3b2013-02-07 02:10:11 +0000290/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200291#define CONFIG_SYS_CS5_START 0xE8000000
Stefan Roese512da3b2013-02-07 02:10:11 +0000292#ifdef CONFIG_A4M2K
293#define CONFIG_SYS_CS5_SIZE 0x00100000
294#else
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200295#define CONFIG_SYS_CS5_SIZE 0x00010000
Stefan Roese512da3b2013-02-07 02:10:11 +0000296#endif
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200297/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
298#define CONFIG_SYS_CS5_CFG 0x0032B900
299
300#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
301#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
Stefan Roese512da3b2013-02-07 02:10:11 +0000302#define CONFIG_SYS_CS1_CFG 0x0008FD00
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200303#define CONFIG_SYS_CS2_CFG 0x0006F90C
304#else /* for pci_clk = 33 MHz */
305#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
306#define CONFIG_SYS_CS1_CFG 0x0001FB00
307#define CONFIG_SYS_CS2_CFG 0x0002F90C
308#endif
309
310#define CONFIG_SYS_CS_BURST 0x00000000
311/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
312/* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
313/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
314#define CONFIG_SYS_CS_DEADCYCLE 0x33030000
315
316#define CONFIG_SYS_RESET_ADDRESS 0xff000000
317
318/*
319 * Environment Configuration
320 */
321
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200322#undef CONFIG_BOOTARGS
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200323
Stefan Roese9071a442013-04-25 23:20:23 +0000324#define CONFIG_SYS_AUTOLOAD "n"
325
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200326#define CONFIG_PREBOOT "echo;" \
327 "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
328 "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
329 "echo"
330
331#undef CONFIG_BOOTARGS
332
Stefan Roese9071a442013-04-25 23:20:23 +0000333#define CONFIG_SYS_FDT_BASE 0xfc1e0000
Mike Looijmansde627902016-07-26 07:34:07 +0200334#define CONFIG_SYS_FDT_SIZE (16<<10)
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200335
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200336#define CONFIG_EXTRA_ENV_SETTINGS \
337 "netdev=eth0\0" \
338 "verify=no\0" \
Stefan Roese512da3b2013-02-07 02:10:11 +0000339 "loadaddr=200000\0" \
340 "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
341 "kernel_addr_r=1000000\0" \
342 "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
343 "fdt_addr_r=1800000\0" \
344 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
345 "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
346 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
347 "rootpath=/opt/eldk-5.2.1/powerpc/" \
348 "core-image-minimal-mtdutils-dropbear-generic\0" \
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200349 "consoledev=ttyPSC0\0" \
350 "nfsargs=setenv bootargs root=/dev/nfs rw " \
351 "nfsroot=${serverip}:${rootpath}\0" \
352 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Stefan Roese5c1617b2013-06-22 16:16:25 +0200353 "mtdargs=setenv bootargs root=/dev/mtdblock8 " \
Stefan Roese9071a442013-04-25 23:20:23 +0000354 "rootfstype=squashfs,jffs2\0" \
355 "addhost=setenv bootargs ${bootargs} " \
356 "hostname=${hostname}\0" \
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200357 "addip=setenv bootargs ${bootargs} " \
358 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
359 ":${hostname}:${netdev}:off panic=1\0" \
360 "addtty=setenv bootargs ${bootargs} " \
361 "console=${consoledev},${baudrate}\0" \
Stefan Roese5c1617b2013-06-22 16:16:25 +0200362 "flash_nfs=run nfsargs addip addtty addmtd addhost;" \
Stefan Roese9071a442013-04-25 23:20:23 +0000363 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Stefan Roese5c1617b2013-06-22 16:16:25 +0200364 "flash_mtd=run mtdargs addip addtty addmtd addhost;" \
Stefan Roese9071a442013-04-25 23:20:23 +0000365 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Stefan Roese5c1617b2013-06-22 16:16:25 +0200366 "flash_self=run ramargs addip addtty addmtd addhost;" \
Stefan Roese512da3b2013-02-07 02:10:11 +0000367 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
368 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
369 "tftp ${fdt_addr_r} ${fdtfile};" \
Stefan Roese5c1617b2013-06-22 16:16:25 +0200370 "run nfsargs addip addtty addmtd addhost;" \
Stefan Roese512da3b2013-02-07 02:10:11 +0000371 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
372 "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
373 "/u-boot-img.bin\0" \
Stefan Roese5c1617b2013-06-22 16:16:25 +0200374 "update=protect off fc000000 fc07ffff;" \
Stefan Roese9071a442013-04-25 23:20:23 +0000375 "era fc000000 fc07ffff;" \
376 "cp.b ${loadaddr} fc000000 ${filesize}\0" \
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200377 "upd=run load;run update\0" \
Stefan Roese5c1617b2013-06-22 16:16:25 +0200378 "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
379 "run mtdargs addip addtty addmtd addhost;" \
380 "fdt addr 1800000;fdt boardsetup;fdt chosen;" \
381 "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
382 "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
383 "erase fc200000 fc6fffff;" \
384 "cp.b 1000000 fc200000 ${filesize}" \
385 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
386 "mtdids=" MTDIDS_DEFAULT "\0" \
387 "mtdparts=" MTDPARTS_DEFAULT "\0" \
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200388 ""
389
390#define CONFIG_BOOTCOMMAND "run flash_mtd"
391
392/*
393 * SPL related defines
394 */
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200395#define CONFIG_SPL_FRAMEWORK
Stefan Roese512da3b2013-02-07 02:10:11 +0000396#define CONFIG_SPL_BOARD_INIT
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200397#define CONFIG_SPL_TEXT_BASE 0xfc000000
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200398
399/* Place BSS for SPL near end of SDRAM */
400#define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
401#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
402
Stefan Roesee1b8d0b2012-08-14 15:04:19 +0200403/* Place patched DT blob (fdt) at this address */
404#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
405
406/* Settings for real U-Boot to be loaded from NOR flash */
407#ifndef __ASSEMBLY__
408extern char __spl_flash_end[];
409#endif
410#define CONFIG_SYS_UBOOT_BASE __spl_flash_end
411#define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
412#define CONFIG_SYS_UBOOT_START 0x1000100
413
414#endif /* __CONFIG_H */