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git01.mediatek.com / filogic / uboot / e70d3623240ec8e1c7e2b9cd8c5570bc7639dc07 / . / arch / arm / dts / fsl-ls1012a.dtsi
blob: 1125e5753b9583a281246af6c14a5604fbf89a5b [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]2/*
3 * Copyright 2016 Freescale Semiconductor
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]4 */
5
6/include/ "skeleton64.dtsi"
7
8/ {
9 compatible = "fsl,ls1012a";
10 interrupt-parent = <&gic>;
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]11
12 sysclk: sysclk {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <100000000>;
16 clock-output-names = "sysclk";
17 };
18
19 gic: interrupt-controller@1400000 {
20 compatible = "arm,gic-400";
21 #interrupt-cells = <3>;
22 interrupt-controller;
23 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
24 <0x0 0x1402000 0 0x2000>, /* GICC */
25 <0x0 0x1404000 0 0x2000>, /* GICH */
26 <0x0 0x1406000 0 0x2000>; /* GICV */
27 interrupts = <1 9 0xf08>;
28 };
29
30 soc {
31 compatible = "simple-bus";
32 #address-cells = <2>;
33 #size-cells = <2>;
34 ranges;
35
36 clockgen: clocking@1ee1000 {
37 compatible = "fsl,ls1012a-clockgen";
38 reg = <0x0 0x1ee1000 0x0 0x1000>;
39 #clock-cells = <2>;
40 clocks = <&sysclk>;
41 };
42
43 dspi0: dspi@2100000 {
44 compatible = "fsl,vf610-dspi";
45 #address-cells = <1>;
46 #size-cells = <0>;
47 reg = <0x0 0x2100000 0x0 0x10000>;
48 interrupts = <0 64 0x4>;
49 clock-names = "dspi";
50 clocks = <&clockgen 4 0>;
51 num-cs = <6>;
52 big-endian;
53 status = "disabled";
54 };
55
Yangbo Lud2710d82016-12-07 11:54:32 +0800[diff] [blame]56 esdhc0: esdhc@1560000 {
57 compatible = "fsl,esdhc";
58 reg = <0x0 0x1560000 0x0 0x10000>;
59 interrupts = <0 62 0x4>;
60 big-endian;
61 bus-width = <4>;
62 };
63
64 esdhc1: esdhc@1580000 {
65 compatible = "fsl,esdhc";
66 reg = <0x0 0x1580000 0x0 0x10000>;
67 interrupts = <0 65 0x4>;
68 big-endian;
69 non-removable;
70 bus-width = <4>;
71 };
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]72
73 i2c0: i2c@2180000 {
74 compatible = "fsl,vf610-i2c";
75 #address-cells = <1>;
76 #size-cells = <0>;
77 reg = <0x0 0x2180000 0x0 0x10000>;
78 interrupts = <0 56 0x4>;
79 clock-names = "i2c";
80 clocks = <&clockgen 4 0>;
81 status = "disabled";
82 };
83
84 i2c1: i2c@2190000 {
85 compatible = "fsl,vf610-i2c";
86 #address-cells = <1>;
87 #size-cells = <0>;
88 reg = <0x0 0x2190000 0x0 0x10000>;
89 interrupts = <0 57 0x4>;
90 clock-names = "i2c";
91 clocks = <&clockgen 4 0>;
92 status = "disabled";
93 };
94
95 duart0: serial@21c0500 {
96 compatible = "fsl,ns16550", "ns16550a";
97 reg = <0x00 0x21c0500 0x0 0x100>;
98 interrupts = <0 54 0x4>;
99 clocks = <&clockgen 4 0>;
100 };
101
102 duart1: serial@21c0600 {
103 compatible = "fsl,ns16550", "ns16550a";
104 reg = <0x00 0x21c0600 0x0 0x100>;
105 interrupts = <0 54 0x4>;
106 clocks = <&clockgen 4 0>;
107 };
108
109 qspi: quadspi@1550000 {
110 compatible = "fsl,vf610-qspi";
111 #address-cells = <1>;
112 #size-cells = <0>;
113 reg = <0x0 0x1550000 0x0 0x10000>,
114 <0x0 0x40000000 0x0 0x4000000>;
115 reg-names = "QuadSPI", "QuadSPI-memory";
Suresh Gupta37e3a652017-02-21 14:26:47 +0530[diff] [blame]116 num-cs = <1>;
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]117 big-endian;
118 status = "disabled";
119 };
120
Minghuan Lian1bbba112016-12-13 14:54:12 +0800[diff] [blame]121 pcie@3400000 {
122 compatible = "fsl,ls-pcie", "snps,dw-pcie";
123 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
124 0x00 0x03480000 0x0 0x40000 /* lut registers */
125 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
126 0x40 0x00000000 0x0 0x20000>; /* configuration space */
127 reg-names = "dbi", "lut", "ctrl", "config";
128 big-endian;
129 #address-cells = <3>;
130 #size-cells = <2>;
131 device_type = "pci";
132 bus-range = <0x0 0xff>;
133 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
134 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
135 };
Tang Yuantianb51f4252016-12-27 10:24:44 +0800[diff] [blame]136
Yuantian Tang019e6e02018-07-13 17:25:29 +0800[diff] [blame]137 sata: sata@3200000 {
138 compatible = "fsl,ls1012a-ahci";
Peng Mae70d3622019-04-17 10:10:49 +0000[diff] [blame^]139 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
140 0x0 0x20140520 0x0 0x4>; /* ecc sata addr */
141 reg-names = "sata-base", "ecc-addr";
Yuantian Tang019e6e02018-07-13 17:25:29 +0800[diff] [blame]142 interrupts = <0 69 4>;
143 clocks = <&clockgen 4 0>;
144 status = "disabled";
145 };
146
Tang Yuantianb51f4252016-12-27 10:24:44 +0800[diff] [blame]147 usb0: usb2@8600000 {
148 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
149 reg = <0x0 0x8600000 0x0 0x1000>;
150 interrupts = <0 139 0x4>;
151 dr_mode = "host";
152 fsl,usb-erratum-a005697;
153 };
154
155 usb1: usb3@2f00000 {
156 compatible = "fsl,layerscape-dwc3";
157 reg = <0x0 0x2f00000 0x0 0x10000>;
158 interrupts = <0 61 0x4>;
159 dr_mode = "host";
160 };
Prabhakar Kushwaha55432502016-06-03 18:41:34 +0530[diff] [blame]161 };
162};