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wdenk0669d4d2002-09-17 20:57:30 +00001/*
wdenk1ebf41e2004-01-02 14:00:00 +00002 * (C) Copyright 2000-2004
wdenk0669d4d2002-09-17 20:57:30 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk2bb11052003-07-17 23:16:40 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk0669d4d2002-09-17 20:57:30 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * mpc8xx.h
26 *
27 * MPC8xx specific definitions
28 */
29
30#ifndef __MPCXX_H__
31#define __MPCXX_H__
32
33
34/*-----------------------------------------------------------------------
35 * Exception offsets (PowerPC standard)
36 */
37#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
38
39
40/*-----------------------------------------------------------------------
41 * SYPCR - System Protection Control Register 11-9
42 */
wdenk4e112c12003-06-03 23:54:09 +000043#define SYPCR_SWTC 0xFFFF0000 /* Software Watchdog Timer Count */
44#define SYPCR_BMT 0x0000FF00 /* Bus Monitor Timing */
wdenk0669d4d2002-09-17 20:57:30 +000045#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */
46#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */
47#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
48#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */
49#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
50
51/*-----------------------------------------------------------------------
52 * SIUMCR - SIU Module Configuration Register 11-6
53 */
54#define SIUMCR_EARB 0x80000000 /* External Arbitration */
55#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */
56#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */
57#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */
58#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */
59#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */
60#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */
61#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */
62#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */
63#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */
64#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */
65#define SIUMCR_DBGC01 0x00200000 /* - " - */
66#define SIUMCR_DBGC10 0x00400000 /* - " - */
67#define SIUMCR_DBGC11 0x00600000 /* - " - */
68#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */
69#define SIUMCR_DBPC01 0x00080000 /* - " - */
70#define SIUMCR_DBPC10 0x00100000 /* - " - */
71#define SIUMCR_DBPC11 0x00180000 /* - " - */
72#define SIUMCR_FRC 0x00020000 /* FRZ pin Configuration */
73#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
74#define SIUMCR_PNCS 0x00008000 /* Parity Non-mem Crtl reg */
75#define SIUMCR_OPAR 0x00004000 /* Odd Parity */
76#define SIUMCR_DPC 0x00002000 /* Data Parity pins Config. */
77#define SIUMCR_MPRE 0x00001000 /* Multi CPU Reserva. Enable */
78#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */
79#define SIUMCR_MLRC01 0x00000400 /* - " - */
80#define SIUMCR_MLRC10 0x00000800 /* - " - */
wdenk4e112c12003-06-03 23:54:09 +000081#define SIUMCR_MLRC11 0x00000C00 /* - " - */
wdenk0669d4d2002-09-17 20:57:30 +000082#define SIUMCR_AEME 0x00000200 /* Asynchro External Master */
83#define SIUMCR_SEME 0x00000100 /* Synchro External Master */
84#define SIUMCR_BSC 0x00000080 /* Byte Select Configuration */
85#define SIUMCR_GB5E 0x00000040 /* GPL_B(5) Enable */
86#define SIUMCR_B2DD 0x00000020 /* Bank 2 Double Drive */
87#define SIUMCR_B3DD 0x00000010 /* Bank 3 Double Drive */
88
89/*-----------------------------------------------------------------------
90 * TBSCR - Time Base Status and Control Register 11-26
91 */
92#define TBSCR_TBIRQ7 0x8000 /* Time Base Interrupt Request 7 */
93#define TBSCR_TBIRQ6 0x4000 /* Time Base Interrupt Request 6 */
94#define TBSCR_TBIRQ5 0x2000 /* Time Base Interrupt Request 5 */
95#define TBSCR_TBIRQ4 0x1000 /* Time Base Interrupt Request 4 */
96#define TBSCR_TBIRQ3 0x0800 /* Time Base Interrupt Request 3 */
97#define TBSCR_TBIRQ2 0x0400 /* Time Base Interrupt Request 2 */
98#define TBSCR_TBIRQ1 0x0200 /* Time Base Interrupt Request 1 */
99#define TBSCR_TBIRQ0 0x0100 /* Time Base Interrupt Request 0 */
100#if 0 /* already in asm/8xx_immap.h */
101#define TBSCR_REFA 0x0080 /* Reference Interrupt Status A */
102#define TBSCR_REFB 0x0040 /* Reference Interrupt Status B */
103#define TBSCR_REFAE 0x0008 /* Second Interrupt Enable A */
104#define TBSCR_REFBE 0x0004 /* Second Interrupt Enable B */
105#define TBSCR_TBF 0x0002 /* Time Base Freeze */
106#define TBSCR_TBE 0x0001 /* Time Base Enable */
107#endif
108
109/*-----------------------------------------------------------------------
110 * PISCR - Periodic Interrupt Status and Control Register 11-31
111 */
112#undef PISCR_PIRQ /* TBD */
113#define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */
114#if 0 /* already in asm/8xx_immap.h */
115#define PISCR_PS 0x0080 /* Periodic interrupt Status */
116#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */
117#define PISCR_PTE 0x0001 /* Periodic Timer Enable */
118#endif
119
120/*-----------------------------------------------------------------------
wdenkd9fce812003-06-28 17:24:46 +0000121 * RSR - Reset Status Register 5-4
122 */
123#define RSR_JTRS 0x01000000 /* JTAG Reset Status */
wdenk2bb11052003-07-17 23:16:40 +0000124#define RSR_DBSRS 0x02000000 /* Debug Port Soft Reset Status */
125#define RSR_DBHRS 0x04000000 /* Debug Port Hard Reset Status */
wdenkd9fce812003-06-28 17:24:46 +0000126#define RSR_CSRS 0x08000000 /* Check Stop Reset Status */
127#define RSR_SWRS 0x10000000 /* Software Watchdog Reset Status*/
128#define RSR_LLRS 0x20000000 /* Loss-of-Lock Reset Status */
129#define RSR_ESRS 0x40000000 /* External Soft Reset Status */
130#define RSR_EHRS 0x80000000 /* External Hard Reset Status */
131
132#define RSR_ALLBITS (RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS)
133
134/*-----------------------------------------------------------------------
wdenkad276f22004-01-04 16:28:35 +0000135 * Newer chips (MPC866 family and MPC87x/88x family) have different
136 * clock distribution system. Their IMMR lower half is >= 0x0800
137 */
138#define MPC8xx_NEW_CLK 0x0800
139
140/*-----------------------------------------------------------------------
wdenk0669d4d2002-09-17 20:57:30 +0000141 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
142 */
wdenkad276f22004-01-04 16:28:35 +0000143/* Newer chips (MPC866/87x/88x et al) defines */
wdenk1ebf41e2004-01-02 14:00:00 +0000144#define PLPRCR_MFN_MSK 0xF8000000 /* Multiplication factor numerator bits */
145#define PLPRCR_MFN_SHIFT 27 /* Multiplication factor numerator shift*/
146#define PLPRCR_MFD_MSK 0x07C00000 /* Multiplication factor denominator bits */
147#define PLPRCR_MFD_SHIFT 22 /* Multiplication factor denominator shift*/
wdenke58b0dc2003-07-27 00:21:01 +0000148#define PLPRCR_S_MSK 0x00300000 /* Multiplication factor integer bits */
wdenk1ebf41e2004-01-02 14:00:00 +0000149#define PLPRCR_S_SHIFT 20 /* Multiplication factor integer shift */
150#define PLPRCR_MFI_MSK 0x000F0000 /* Multiplication factor integer bits */
151#define PLPRCR_MFI_SHIFT 16 /* Multiplication factor integer shift */
wdenkad276f22004-01-04 16:28:35 +0000152
153#define PLPRCR_PDF_MSK 0x0000001E /* Predivision Factor bits */
154#define PLPRCR_PDF_SHIFT 1 /* Predivision Factor shift value */
155#define PLPRCR_DBRMO 0x00000001 /* DPLL BRM Order bit */
156
157/* Multiplication factor + PDF bits */
158#define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \
159 PLPRCR_MFD_MSK | \
160 PLPRCR_S_MSK | \
161 PLPRCR_MFI_MSK | \
162 PLPRCR_PDF_MSK)
163
164/* Older chips (MPC860/862 et al) defines */
wdenk1ebf41e2004-01-02 14:00:00 +0000165#define PLPRCR_MF_MSK 0xFFF00000 /* Multiplication factor bits */
166#define PLPRCR_MF_SHIFT 20 /* Multiplication factor shift value */
wdenkad276f22004-01-04 16:28:35 +0000167
wdenk0669d4d2002-09-17 20:57:30 +0000168#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */
wdenk0669d4d2002-09-17 20:57:30 +0000169#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */
wdenkad276f22004-01-04 16:28:35 +0000170
wdenk0669d4d2002-09-17 20:57:30 +0000171#define PLPRCR_LPM_MSK 0x00000300 /* Low Power Mode mask */
172#define PLPRCR_LPM_NORMAL 0x00000000 /* normal power management mode */
173#define PLPRCR_LPM_DOZE 0x00000100 /* doze power management mode */
174#define PLPRCR_LPM_SLEEP 0x00000200 /* sleep power management mode */
175#define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode */
176#define PLPRCR_LPM_DOWN 0x00000300 /* down power management mode */
wdenkad276f22004-01-04 16:28:35 +0000177
178/* Common defines */
179#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */
180#define PLPRCR_CSRC 0x00000400 /* Clock Source */
181
wdenk0669d4d2002-09-17 20:57:30 +0000182#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */
183#define PLPRCR_LOLRE 0x00000040 /* Loss Of Lock Reset Enable */
184#define PLPRCR_FIOPD 0x00000020 /* Force I/O Pull Down */
185
186/*-----------------------------------------------------------------------
187 * SCCR - System Clock and reset Control Register 15-27
188 */
189#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
190#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
191#define SCCR_COM10 0x40000000 /* reserved */
192#define SCCR_COM11 0x60000000 /* CLKOUT output buffer disabled */
193#define SCCR_TBS 0x02000000 /* Time Base Source */
194#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
195#define SCCR_RTSEL 0x00800000 /* RTC circuit input source select */
196#define SCCR_CRQEN 0x00400000 /* CPM Request Enable */
197#define SCCR_PRQEN 0x00200000 /* Power Management Request Enable */
198#define SCCR_EBDF00 0x00000000 /* CLKOUT is GCLK2 / 1 (normal op.) */
199#define SCCR_EBDF01 0x00020000 /* CLKOUT is GCLK2 / 2 */
200#define SCCR_EBDF10 0x00040000 /* reserved */
201#define SCCR_EBDF11 0x00060000 /* reserved */
202#define SCCR_DFSYNC00 0x00000000 /* SyncCLK division by 1 (normal op.) */
203#define SCCR_DFSYNC01 0x00002000 /* SyncCLK division by 4 */
204#define SCCR_DFSYNC10 0x00004000 /* SyncCLK division by 16 */
205#define SCCR_DFSYNC11 0x00006000 /* SyncCLK division by 64 */
206#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 1 (normal op.) */
207#define SCCR_DFBRG01 0x00000800 /* BRGCLK division by 4 */
208#define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */
209#define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */
210#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
wdenke7047de2004-04-15 21:31:56 +0000211#define SCCR_DFNL001 0x00000100 /* Division by 4 */
212#define SCCR_DFNL010 0x00000200 /* Division by 8 */
213#define SCCR_DFNL011 0x00000300 /* Division by 16 */
214#define SCCR_DFNL100 0x00000400 /* Division by 32 */
215#define SCCR_DFNL101 0x00000500 /* Division by 64 */
216#define SCCR_DFNL110 0x00000600 /* Division by 128 */
wdenk0669d4d2002-09-17 20:57:30 +0000217#define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */
218#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
219#define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */
220#define SCCR_DFNH111 0x000000E0 /* reserved */
221#define SCCR_DFLCD000 0x00000000 /* Division by 1 (default = minimum) */
222#define SCCR_DFLCD001 0x00000004 /* Division by 2 */
223#define SCCR_DFLCD010 0x00000008 /* Division by 4 */
224#define SCCR_DFLCD011 0x0000000C /* Division by 8 */
225#define SCCR_DFLCD100 0x00000010 /* Division by 16 */
226#define SCCR_DFLCD101 0x00000014 /* Division by 32 */
227#define SCCR_DFLCD110 0x00000018 /* Division by 64 (maximum) */
228#define SCCR_DFLCD111 0x0000001C /* reserved */
229#define SCCR_DFALCD00 0x00000000 /* Division by 1 (default = minimum) */
230#define SCCR_DFALCD01 0x00000001 /* Division by 3 */
231#define SCCR_DFALCD10 0x00000002 /* Division by 5 */
232#define SCCR_DFALCD11 0x00000003 /* Division by 7 (maximum) */
233
234
235/*-----------------------------------------------------------------------
236 * BR - Memory Controler: Base Register 16-9
237 */
wdenk4e112c12003-06-03 23:54:09 +0000238#define BR_BA_MSK 0xFFFF8000 /* Base Address Mask */
wdenk0669d4d2002-09-17 20:57:30 +0000239#define BR_AT_MSK 0x00007000 /* Address Type Mask */
wdenk4e112c12003-06-03 23:54:09 +0000240#define BR_PS_MSK 0x00000C00 /* Port Size Mask */
wdenk0669d4d2002-09-17 20:57:30 +0000241#define BR_PS_32 0x00000000 /* 32 bit port size */
242#define BR_PS_16 0x00000800 /* 16 bit port size */
243#define BR_PS_8 0x00000400 /* 8 bit port size */
244#define BR_PARE 0x00000200 /* Parity Enable */
245#define BR_WP 0x00000100 /* Write Protect */
wdenk4e112c12003-06-03 23:54:09 +0000246#define BR_MS_MSK 0x000000C0 /* Machine Select Mask */
wdenk0669d4d2002-09-17 20:57:30 +0000247#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
248#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
wdenk4e112c12003-06-03 23:54:09 +0000249#define BR_MS_UPMB 0x000000C0 /* U.P.M.B Machine Select */
wdenk0669d4d2002-09-17 20:57:30 +0000250#define BR_V 0x00000001 /* Bank Valid */
251
252/*-----------------------------------------------------------------------
253 * OR - Memory Controler: Option Register 16-11
254 */
wdenk4e112c12003-06-03 23:54:09 +0000255#define OR_AM_MSK 0xFFFF8000 /* Address Mask Mask */
wdenk0669d4d2002-09-17 20:57:30 +0000256#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */
257#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */
258 /* Address Multiplex */
259#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */
260#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */
261#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */
262#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */
263#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
264#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
265#define OR_BI 0x00000100 /* Burst inhibit */
wdenk4e112c12003-06-03 23:54:09 +0000266#define OR_SCY_MSK 0x000000F0 /* Cycle Lenght in Clocks */
wdenk0669d4d2002-09-17 20:57:30 +0000267#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
268#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
269#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
270#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
271#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
272#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
273#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
274#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
275#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
276#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
wdenk4e112c12003-06-03 23:54:09 +0000277#define OR_SCY_10_CLK 0x000000A0 /* 10 clock cycles wait states */
278#define OR_SCY_11_CLK 0x000000B0 /* 11 clock cycles wait states */
279#define OR_SCY_12_CLK 0x000000C0 /* 12 clock cycles wait states */
280#define OR_SCY_13_CLK 0x000000D0 /* 13 clock cycles wait states */
281#define OR_SCY_14_CLK 0x000000E0 /* 14 clock cycles wait states */
282#define OR_SCY_15_CLK 0x000000F0 /* 15 clock cycles wait states */
wdenk0669d4d2002-09-17 20:57:30 +0000283#define OR_SETA 0x00000008 /* External Transfer Acknowledge */
284#define OR_TRLX 0x00000004 /* Timing Relaxed */
285#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */
286
287
288/*-----------------------------------------------------------------------
289 * MPTPR - Memory Periodic Timer Prescaler Register 16-17
290 */
wdenk4e112c12003-06-03 23:54:09 +0000291#define MPTPR_PTP_MSK 0xFF00 /* Periodic Timers Prescaler Mask */
wdenk0669d4d2002-09-17 20:57:30 +0000292#define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */
293#define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */
294#define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */
295#define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */
296#define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */
297#define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */
298
299/*-----------------------------------------------------------------------
300 * MCR - Memory Command Register
301 */
302#define MCR_OP_WRITE 0x00000000 /* WRITE command */
wdenk2bb11052003-07-17 23:16:40 +0000303#define MCR_OP_READ 0x40000000 /* READ command */
304#define MCR_OP_RUN 0x80000000 /* RUN command */
wdenk0669d4d2002-09-17 20:57:30 +0000305#define MCR_UPM_A 0x00000000 /* Select UPM A */
306#define MCR_UPM_B 0x00800000 /* Select UPM B */
307#define MCR_MB_CS0 0x00000000 /* Use Chip Select /CS0 */
308#define MCR_MB_CS1 0x00002000 /* Use Chip Select /CS1 */
309#define MCR_MB_CS2 0x00004000 /* Use Chip Select /CS2 */
310#define MCR_MB_CS3 0x00006000 /* Use Chip Select /CS3 */
311#define MCR_MB_CS4 0x00008000 /* Use Chip Select /CS4 */
312#define MCR_MB_CS5 0x0000A000 /* Use Chip Select /CS5 */
313#define MCR_MB_CS6 0x0000C000 /* Use Chip Select /CS6 */
314#define MCR_MB_CS7 0x0000E000 /* Use Chip Select /CS7 */
315#define MCR_MLCF(n) (((n)&0xF)<<8) /* Memory Command Loop Count Field */
316#define MCR_MAD(addr) ((addr)&0x3F) /* Memory Array Index */
317
318/*-----------------------------------------------------------------------
319 * Machine A Mode Register 16-13
320 */
wdenk4e112c12003-06-03 23:54:09 +0000321#define MAMR_PTA_MSK 0xFF000000 /* Periodic Timer A period mask */
wdenk0669d4d2002-09-17 20:57:30 +0000322#define MAMR_PTA_SHIFT 0x00000018 /* Periodic Timer A period shift */
323#define MAMR_PTAE 0x00800000 /* Periodic Timer A Enable */
324#define MAMR_AMA_MSK 0x00700000 /* Addess Multiplexing size A */
325#define MAMR_AMA_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
326#define MAMR_AMA_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */
327#define MAMR_AMA_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */
328#define MAMR_AMA_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */
329#define MAMR_AMA_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */
330#define MAMR_AMA_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */
331#define MAMR_DSA_MSK 0x00060000 /* Disable Timer period mask */
332#define MAMR_DSA_1_CYCL 0x00000000 /* 1 cycle Disable Period */
333#define MAMR_DSA_2_CYCL 0x00020000 /* 2 cycle Disable Period */
334#define MAMR_DSA_3_CYCL 0x00040000 /* 3 cycle Disable Period */
335#define MAMR_DSA_4_CYCL 0x00060000 /* 4 cycle Disable Period */
wdenk4e112c12003-06-03 23:54:09 +0000336#define MAMR_G0CLA_MSK 0x0000E000 /* General Line 0 Control A */
wdenk0669d4d2002-09-17 20:57:30 +0000337#define MAMR_G0CLA_A12 0x00000000 /* General Line 0 : A12 */
338#define MAMR_G0CLA_A11 0x00002000 /* General Line 0 : A11 */
339#define MAMR_G0CLA_A10 0x00004000 /* General Line 0 : A10 */
340#define MAMR_G0CLA_A9 0x00006000 /* General Line 0 : A9 */
341#define MAMR_G0CLA_A8 0x00008000 /* General Line 0 : A8 */
wdenk4e112c12003-06-03 23:54:09 +0000342#define MAMR_G0CLA_A7 0x0000A000 /* General Line 0 : A7 */
343#define MAMR_G0CLA_A6 0x0000C000 /* General Line 0 : A6 */
344#define MAMR_G0CLA_A5 0x0000E000 /* General Line 0 : A5 */
wdenk0669d4d2002-09-17 20:57:30 +0000345#define MAMR_GPL_A4DIS 0x00001000 /* GPL_A4 ouput line Disable */
wdenk4e112c12003-06-03 23:54:09 +0000346#define MAMR_RLFA_MSK 0x00000F00 /* Read Loop Field A mask */
wdenk0669d4d2002-09-17 20:57:30 +0000347#define MAMR_RLFA_1X 0x00000100 /* The Read Loop is executed 1 time */
348#define MAMR_RLFA_2X 0x00000200 /* The Read Loop is executed 2 times */
349#define MAMR_RLFA_3X 0x00000300 /* The Read Loop is executed 3 times */
350#define MAMR_RLFA_4X 0x00000400 /* The Read Loop is executed 4 times */
351#define MAMR_RLFA_5X 0x00000500 /* The Read Loop is executed 5 times */
352#define MAMR_RLFA_6X 0x00000600 /* The Read Loop is executed 6 times */
353#define MAMR_RLFA_7X 0x00000700 /* The Read Loop is executed 7 times */
354#define MAMR_RLFA_8X 0x00000800 /* The Read Loop is executed 8 times */
355#define MAMR_RLFA_9X 0x00000900 /* The Read Loop is executed 9 times */
wdenk4e112c12003-06-03 23:54:09 +0000356#define MAMR_RLFA_10X 0x00000A00 /* The Read Loop is executed 10 times */
357#define MAMR_RLFA_11X 0x00000B00 /* The Read Loop is executed 11 times */
358#define MAMR_RLFA_12X 0x00000C00 /* The Read Loop is executed 12 times */
359#define MAMR_RLFA_13X 0x00000D00 /* The Read Loop is executed 13 times */
360#define MAMR_RLFA_14X 0x00000E00 /* The Read Loop is executed 14 times */
361#define MAMR_RLFA_15X 0x00000F00 /* The Read Loop is executed 15 times */
wdenk0669d4d2002-09-17 20:57:30 +0000362#define MAMR_RLFA_16X 0x00000000 /* The Read Loop is executed 16 times */
wdenk4e112c12003-06-03 23:54:09 +0000363#define MAMR_WLFA_MSK 0x000000F0 /* Write Loop Field A mask */
wdenk0669d4d2002-09-17 20:57:30 +0000364#define MAMR_WLFA_1X 0x00000010 /* The Write Loop is executed 1 time */
365#define MAMR_WLFA_2X 0x00000020 /* The Write Loop is executed 2 times */
366#define MAMR_WLFA_3X 0x00000030 /* The Write Loop is executed 3 times */
367#define MAMR_WLFA_4X 0x00000040 /* The Write Loop is executed 4 times */
368#define MAMR_WLFA_5X 0x00000050 /* The Write Loop is executed 5 times */
369#define MAMR_WLFA_6X 0x00000060 /* The Write Loop is executed 6 times */
370#define MAMR_WLFA_7X 0x00000070 /* The Write Loop is executed 7 times */
371#define MAMR_WLFA_8X 0x00000080 /* The Write Loop is executed 8 times */
372#define MAMR_WLFA_9X 0x00000090 /* The Write Loop is executed 9 times */
wdenk4e112c12003-06-03 23:54:09 +0000373#define MAMR_WLFA_10X 0x000000A0 /* The Write Loop is executed 10 times */
374#define MAMR_WLFA_11X 0x000000B0 /* The Write Loop is executed 11 times */
375#define MAMR_WLFA_12X 0x000000C0 /* The Write Loop is executed 12 times */
376#define MAMR_WLFA_13X 0x000000D0 /* The Write Loop is executed 13 times */
377#define MAMR_WLFA_14X 0x000000E0 /* The Write Loop is executed 14 times */
378#define MAMR_WLFA_15X 0x000000F0 /* The Write Loop is executed 15 times */
wdenk0669d4d2002-09-17 20:57:30 +0000379#define MAMR_WLFA_16X 0x00000000 /* The Write Loop is executed 16 times */
wdenk4e112c12003-06-03 23:54:09 +0000380#define MAMR_TLFA_MSK 0x0000000F /* Timer Loop Field A mask */
wdenk0669d4d2002-09-17 20:57:30 +0000381#define MAMR_TLFA_1X 0x00000001 /* The Timer Loop is executed 1 time */
382#define MAMR_TLFA_2X 0x00000002 /* The Timer Loop is executed 2 times */
383#define MAMR_TLFA_3X 0x00000003 /* The Timer Loop is executed 3 times */
384#define MAMR_TLFA_4X 0x00000004 /* The Timer Loop is executed 4 times */
385#define MAMR_TLFA_5X 0x00000005 /* The Timer Loop is executed 5 times */
386#define MAMR_TLFA_6X 0x00000006 /* The Timer Loop is executed 6 times */
387#define MAMR_TLFA_7X 0x00000007 /* The Timer Loop is executed 7 times */
388#define MAMR_TLFA_8X 0x00000008 /* The Timer Loop is executed 8 times */
389#define MAMR_TLFA_9X 0x00000009 /* The Timer Loop is executed 9 times */
wdenk4e112c12003-06-03 23:54:09 +0000390#define MAMR_TLFA_10X 0x0000000A /* The Timer Loop is executed 10 times */
391#define MAMR_TLFA_11X 0x0000000B /* The Timer Loop is executed 11 times */
392#define MAMR_TLFA_12X 0x0000000C /* The Timer Loop is executed 12 times */
393#define MAMR_TLFA_13X 0x0000000D /* The Timer Loop is executed 13 times */
394#define MAMR_TLFA_14X 0x0000000E /* The Timer Loop is executed 14 times */
395#define MAMR_TLFA_15X 0x0000000F /* The Timer Loop is executed 15 times */
wdenk0669d4d2002-09-17 20:57:30 +0000396#define MAMR_TLFA_16X 0x00000000 /* The Timer Loop is executed 16 times */
397
398/*-----------------------------------------------------------------------
399 * Machine B Mode Register 16-13
400 */
wdenk2bb11052003-07-17 23:16:40 +0000401#define MBMR_PTB_MSK 0xFF000000 /* Periodic Timer B period mask */
402#define MBMR_PTB_SHIFT 0x00000018 /* Periodic Timer B period shift */
403#define MBMR_PTBE 0x00800000 /* Periodic Timer B Enable */
404#define MBMR_AMB_MSK 0x00700000 /* Addess Multiplex size B */
405#define MBMR_AMB_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
406#define MBMR_AMB_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */
407#define MBMR_AMB_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */
408#define MBMR_AMB_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */
409#define MBMR_AMB_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */
410#define MBMR_AMB_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */
411#define MBMR_DSB_MSK 0x00060000 /* Disable Timer period mask */
412#define MBMR_DSB_1_CYCL 0x00000000 /* 1 cycle Disable Period */
413#define MBMR_DSB_2_CYCL 0x00020000 /* 2 cycle Disable Period */
414#define MBMR_DSB_3_CYCL 0x00040000 /* 3 cycle Disable Period */
415#define MBMR_DSB_4_CYCL 0x00060000 /* 4 cycle Disable Period */
416#define MBMR_G0CLB_MSK 0x0000E000 /* General Line 0 Control B */
417#define MBMR_G0CLB_A12 0x00000000 /* General Line 0 : A12 */
418#define MBMR_G0CLB_A11 0x00002000 /* General Line 0 : A11 */
419#define MBMR_G0CLB_A10 0x00004000 /* General Line 0 : A10 */
420#define MBMR_G0CLB_A9 0x00006000 /* General Line 0 : A9 */
421#define MBMR_G0CLB_A8 0x00008000 /* General Line 0 : A8 */
422#define MBMR_G0CLB_A7 0x0000A000 /* General Line 0 : A7 */
423#define MBMR_G0CLB_A6 0x0000C000 /* General Line 0 : A6 */
424#define MBMR_G0CLB_A5 0x0000E000 /* General Line 0 : A5 */
425#define MBMR_GPL_B4DIS 0x00001000 /* GPL_B4 ouput line Disable */
426#define MBMR_RLFB_MSK 0x00000F00 /* Read Loop Field B mask */
427#define MBMR_RLFB_1X 0x00000100 /* The Read Loop is executed 1 time */
428#define MBMR_RLFB_2X 0x00000200 /* The Read Loop is executed 2 times */
429#define MBMR_RLFB_3X 0x00000300 /* The Read Loop is executed 3 times */
430#define MBMR_RLFB_4X 0x00000400 /* The Read Loop is executed 4 times */
431#define MBMR_RLFB_5X 0x00000500 /* The Read Loop is executed 5 times */
432#define MBMR_RLFB_6X 0x00000600 /* The Read Loop is executed 6 times */
433#define MBMR_RLFB_7X 0x00000700 /* The Read Loop is executed 7 times */
434#define MBMR_RLFB_8X 0x00000800 /* The Read Loop is executed 8 times */
435#define MBMR_RLFB_9X 0x00000900 /* The Read Loop is executed 9 times */
436#define MBMR_RLFB_10X 0x00000A00 /* The Read Loop is executed 10 times */
437#define MBMR_RLFB_11X 0x00000B00 /* The Read Loop is executed 11 times */
438#define MBMR_RLFB_12X 0x00000C00 /* The Read Loop is executed 12 times */
439#define MBMR_RLFB_13X 0x00000D00 /* The Read Loop is executed 13 times */
440#define MBMR_RLFB_14X 0x00000E00 /* The Read Loop is executed 14 times */
441#define MBMR_RLFB_15X 0x00000f00 /* The Read Loop is executed 15 times */
442#define MBMR_RLFB_16X 0x00000000 /* The Read Loop is executed 16 times */
443#define MBMR_WLFB_MSK 0x000000F0 /* Write Loop Field B mask */
444#define MBMR_WLFB_1X 0x00000010 /* The Write Loop is executed 1 time */
445#define MBMR_WLFB_2X 0x00000020 /* The Write Loop is executed 2 times */
446#define MBMR_WLFB_3X 0x00000030 /* The Write Loop is executed 3 times */
447#define MBMR_WLFB_4X 0x00000040 /* The Write Loop is executed 4 times */
448#define MBMR_WLFB_5X 0x00000050 /* The Write Loop is executed 5 times */
449#define MBMR_WLFB_6X 0x00000060 /* The Write Loop is executed 6 times */
450#define MBMR_WLFB_7X 0x00000070 /* The Write Loop is executed 7 times */
451#define MBMR_WLFB_8X 0x00000080 /* The Write Loop is executed 8 times */
452#define MBMR_WLFB_9X 0x00000090 /* The Write Loop is executed 9 times */
453#define MBMR_WLFB_10X 0x000000A0 /* The Write Loop is executed 10 times */
454#define MBMR_WLFB_11X 0x000000B0 /* The Write Loop is executed 11 times */
455#define MBMR_WLFB_12X 0x000000C0 /* The Write Loop is executed 12 times */
456#define MBMR_WLFB_13X 0x000000D0 /* The Write Loop is executed 13 times */
457#define MBMR_WLFB_14X 0x000000E0 /* The Write Loop is executed 14 times */
458#define MBMR_WLFB_15X 0x000000F0 /* The Write Loop is executed 15 times */
459#define MBMR_WLFB_16X 0x00000000 /* The Write Loop is executed 16 times */
460#define MBMR_TLFB_MSK 0x0000000F /* Timer Loop Field B mask */
461#define MBMR_TLFB_1X 0x00000001 /* The Timer Loop is executed 1 time */
462#define MBMR_TLFB_2X 0x00000002 /* The Timer Loop is executed 2 times */
463#define MBMR_TLFB_3X 0x00000003 /* The Timer Loop is executed 3 times */
464#define MBMR_TLFB_4X 0x00000004 /* The Timer Loop is executed 4 times */
465#define MBMR_TLFB_5X 0x00000005 /* The Timer Loop is executed 5 times */
466#define MBMR_TLFB_6X 0x00000006 /* The Timer Loop is executed 6 times */
467#define MBMR_TLFB_7X 0x00000007 /* The Timer Loop is executed 7 times */
468#define MBMR_TLFB_8X 0x00000008 /* The Timer Loop is executed 8 times */
469#define MBMR_TLFB_9X 0x00000009 /* The Timer Loop is executed 9 times */
470#define MBMR_TLFB_10X 0x0000000A /* The Timer Loop is executed 10 times */
471#define MBMR_TLFB_11X 0x0000000B /* The Timer Loop is executed 11 times */
472#define MBMR_TLFB_12X 0x0000000C /* The Timer Loop is executed 12 times */
473#define MBMR_TLFB_13X 0x0000000D /* The Timer Loop is executed 13 times */
474#define MBMR_TLFB_14X 0x0000000E /* The Timer Loop is executed 14 times */
475#define MBMR_TLFB_15X 0x0000000F /* The Timer Loop is executed 15 times */
476#define MBMR_TLFB_16X 0x00000000 /* The Timer Loop is executed 16 times */
wdenk0669d4d2002-09-17 20:57:30 +0000477
478/*-----------------------------------------------------------------------
479 * Timer Global Configuration Register 18-8
480 */
481#define TGCR_CAS4 0x8000 /* Cascade Timer 3 and 4 */
482#define TGCR_FRZ4 0x4000 /* Freeze timer 4 */
wdenk2bb11052003-07-17 23:16:40 +0000483#define TGCR_STP4 0x2000 /* Stop timer 4 */
484#define TGCR_RST4 0x1000 /* Reset timer 4 */
wdenk0669d4d2002-09-17 20:57:30 +0000485#define TGCR_GM2 0x0800 /* Gate Mode for Pin 2 */
486#define TGCR_FRZ3 0x0400 /* Freeze timer 3 */
wdenk2bb11052003-07-17 23:16:40 +0000487#define TGCR_STP3 0x0200 /* Stop timer 3 */
488#define TGCR_RST3 0x0100 /* Reset timer 3 */
wdenk0669d4d2002-09-17 20:57:30 +0000489#define TGCR_CAS2 0x0080 /* Cascade Timer 1 and 2 */
490#define TGCR_FRZ2 0x0040 /* Freeze timer 2 */
wdenk2bb11052003-07-17 23:16:40 +0000491#define TGCR_STP2 0x0020 /* Stop timer 2 */
492#define TGCR_RST2 0x0010 /* Reset timer 2 */
wdenk0669d4d2002-09-17 20:57:30 +0000493#define TGCR_GM1 0x0008 /* Gate Mode for Pin 1 */
494#define TGCR_FRZ1 0x0004 /* Freeze timer 1 */
wdenk2bb11052003-07-17 23:16:40 +0000495#define TGCR_STP1 0x0002 /* Stop timer 1 */
496#define TGCR_RST1 0x0001 /* Reset timer 1 */
wdenk0669d4d2002-09-17 20:57:30 +0000497
498
499/*-----------------------------------------------------------------------
500 * Timer Mode Register 18-9
501 */
wdenk2bb11052003-07-17 23:16:40 +0000502#define TMR_PS_MSK 0xFF00 /* Prescaler Value */
503#define TMR_PS_SHIFT 8 /* Prescaler position */
504#define TMR_CE_MSK 0x00C0 /* Capture Edge and Enable Interrupt */
505#define TMR_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event */
506#define TMR_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
507#define TMR_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
508#define TMR_CE_ANY 0x00C0 /* Capture on any TINx edge */
509#define TMR_OM 0x0020 /* Output Mode */
510#define TMR_ORI 0x0010 /* Output Reference Interrupt Enable */
511#define TMR_FRR 0x0008 /* Free Run/Restart */
512#define TMR_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
513#define TMR_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
514#define TMR_ICLK_IN_GEN 0x0002 /* Internal General system clock */
515#define TMR_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16 */
516#define TMR_ICLK_TIN_PIN 0x0006 /* TINx pin */
517#define TMR_GE 0x0001 /* Gate Enable */
wdenk0669d4d2002-09-17 20:57:30 +0000518
519
520/*-----------------------------------------------------------------------
521 * I2C Controller Registers
522 */
wdenk2bb11052003-07-17 23:16:40 +0000523#define I2MOD_REVD 0x20 /* Reverese Data */
wdenk0669d4d2002-09-17 20:57:30 +0000524#define I2MOD_GCD 0x10 /* General Call Disable */
525#define I2MOD_FLT 0x08 /* Clock Filter */
526#define I2MOD_PDIV32 0x00 /* Pre-Divider 32 */
527#define I2MOD_PDIV16 0x02 /* Pre-Divider 16 */
wdenk2bb11052003-07-17 23:16:40 +0000528#define I2MOD_PDIV8 0x04 /* Pre-Divider 8 */
529#define I2MOD_PDIV4 0x06 /* Pre-Divider 4 */
wdenk0669d4d2002-09-17 20:57:30 +0000530#define I2MOD_EN 0x01 /* Enable */
531
wdenk2bb11052003-07-17 23:16:40 +0000532#define I2CER_TXE 0x10 /* Tx Error */
wdenk0669d4d2002-09-17 20:57:30 +0000533#define I2CER_BSY 0x04 /* Busy Condition */
534#define I2CER_TXB 0x02 /* Tx Buffer Transmitted */
535#define I2CER_RXB 0x01 /* Rx Buffer Received */
536#define I2CER_ALL (I2CER_TXE | I2CER_BSY | I2CER_TXB | I2CER_RXB)
537
538#define I2COM_STR 0x80 /* Start Transmit */
539#define I2COM_MASTER 0x01 /* Master mode */
540
541/*-----------------------------------------------------------------------
542 * SPI Controller Registers 31-10
543 */
544#define SPI_EMASK 0x37 /* Event Mask */
545#define SPI_MME 0x20 /* Multi-Master Error */
546#define SPI_TXE 0x10 /* Transmit Error */
547#define SPI_BSY 0x04 /* Busy */
548#define SPI_TXB 0x02 /* Tx Buffer Empty */
549#define SPI_RXB 0x01 /* RX Buffer full/closed */
550
551#define SPI_STR 0x80 /* SPCOM: Start transmit */
552
553/*-----------------------------------------------------------------------
554 * PCMCIA Interface General Control Register 17-12
555 */
wdenk2bb11052003-07-17 23:16:40 +0000556#define PCMCIA_GCRX_CXRESET 0x00000040
wdenk0669d4d2002-09-17 20:57:30 +0000557#define PCMCIA_GCRX_CXOE 0x00000080
558
559#define PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
560#define PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
wdenk4e112c12003-06-03 23:54:09 +0000561#define PCMCIA_VS_MASK(slot) (0xC0000000 >> (slot << 4))
wdenk0669d4d2002-09-17 20:57:30 +0000562#define PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
563
564#define PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
565#define PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
566#define PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
567#define PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
568#define PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
569#define PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
570#define PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
571#define PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
572#define PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
573#define PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
574#define PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
575
576/*-----------------------------------------------------------------------
577 * PCMCIA Option Register Definitions
578 *
579 * Bank Sizes:
580 */
wdenk2bb11052003-07-17 23:16:40 +0000581#define PCMCIA_BSIZE_1 0x00000000 /* Bank size: 1 Bytes */
582#define PCMCIA_BSIZE_2 0x08000000 /* Bank size: 2 Bytes */
583#define PCMCIA_BSIZE_4 0x18000000 /* Bank size: 4 Bytes */
584#define PCMCIA_BSIZE_8 0x10000000 /* Bank size: 8 Bytes */
585#define PCMCIA_BSIZE_16 0x30000000 /* Bank size: 16 Bytes */
586#define PCMCIA_BSIZE_32 0x38000000 /* Bank size: 32 Bytes */
587#define PCMCIA_BSIZE_64 0x28000000 /* Bank size: 64 Bytes */
588#define PCMCIA_BSIZE_128 0x20000000 /* Bank size: 128 Bytes */
589#define PCMCIA_BSIZE_256 0x60000000 /* Bank size: 256 Bytes */
590#define PCMCIA_BSIZE_512 0x68000000 /* Bank size: 512 Bytes */
591#define PCMCIA_BSIZE_1K 0x78000000 /* Bank size: 1 kB */
592#define PCMCIA_BSIZE_2K 0x70000000 /* Bank size: 2 kB */
593#define PCMCIA_BSIZE_4K 0x50000000 /* Bank size: 4 kB */
594#define PCMCIA_BSIZE_8K 0x58000000 /* Bank size: 8 kB */
wdenk0669d4d2002-09-17 20:57:30 +0000595#define PCMCIA_BSIZE_16K 0x48000000 /* Bank size: 16 kB */
596#define PCMCIA_BSIZE_32K 0x40000000 /* Bank size: 32 kB */
597#define PCMCIA_BSIZE_64K 0xC0000000 /* Bank size: 64 kB */
598#define PCMCIA_BSIZE_128K 0xC8000000 /* Bank size: 128 kB */
599#define PCMCIA_BSIZE_256K 0xD8000000 /* Bank size: 256 kB */
600#define PCMCIA_BSIZE_512K 0xD0000000 /* Bank size: 512 kB */
wdenk2bb11052003-07-17 23:16:40 +0000601#define PCMCIA_BSIZE_1M 0xF0000000 /* Bank size: 1 MB */
602#define PCMCIA_BSIZE_2M 0xF8000000 /* Bank size: 2 MB */
603#define PCMCIA_BSIZE_4M 0xE8000000 /* Bank size: 4 MB */
604#define PCMCIA_BSIZE_8M 0xE0000000 /* Bank size: 8 MB */
wdenk0669d4d2002-09-17 20:57:30 +0000605#define PCMCIA_BSIZE_16M 0xA0000000 /* Bank size: 16 MB */
606#define PCMCIA_BSIZE_32M 0xA8000000 /* Bank size: 32 MB */
607#define PCMCIA_BSIZE_64M 0xB8000000 /* Bank size: 64 MB */
608
609/* PCMCIA Timing */
wdenk2bb11052003-07-17 23:16:40 +0000610#define PCMCIA_SHT(t) ((t & 0x0F)<<16) /* Strobe Hold Time */
wdenk0669d4d2002-09-17 20:57:30 +0000611#define PCMCIA_SST(t) ((t & 0x0F)<<12) /* Strobe Setup Time */
612#define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length */
613
614/* PCMCIA Port Sizes */
615#define PCMCIA_PPS_8 0x00000000 /* 8 bit port size */
616#define PCMCIA_PPS_16 0x00000040 /* 16 bit port size */
617
618/* PCMCIA Region Select */
619#define PCMCIA_PRS_MEM 0x00000000 /* Common Memory Space */
620#define PCMCIA_PRS_ATTR 0x00000010 /* Attribute Space */
wdenk2bb11052003-07-17 23:16:40 +0000621#define PCMCIA_PRS_IO 0x00000018 /* I/O Space */
622#define PCMCIA_PRS_DMA 0x00000020 /* DMA, normal transfer */
wdenk0669d4d2002-09-17 20:57:30 +0000623#define PCMCIA_PRS_DMA_LAST 0x00000028 /* DMA, last transactn */
wdenk2bb11052003-07-17 23:16:40 +0000624#define PCMCIA_PRS_CEx 0x00000030 /* A[22:23] ==> CE1,CE2 */
wdenk0669d4d2002-09-17 20:57:30 +0000625
626#define PCMCIA_PSLOT_A 0x00000000 /* Slot A */
627#define PCMCIA_PSLOT_B 0x00000004 /* Slot B */
628#define PCMCIA_WPROT 0x00000002 /* Write Protect */
629#define PCMCIA_PV 0x00000001 /* Valid Bit */
630
631#define UPMA 0x00000000
632#define UPMB 0x00800000
633
634#endif /* __MPCXX_H__ */