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git01.mediatek.com / filogic / uboot / e6b57eb31fe0583080eafbfe76eacccd7fa3efbe / . / arch / arm / dts / nuvoton-npcm750-evb.dts
blob: d4667a1df46f8fc401d3f3c065665f72683549f5 [file] [log] [blame]
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
3// Copyright 2018 Google, Inc.
4
5/dts-v1/;
6#include "nuvoton-npcm750.dtsi"
7#include "dt-bindings/gpio/gpio.h"
8#include "nuvoton-npcm750-pincfg-evb.dtsi"
9
10/ {
11 model = "Nuvoton npcm750 Development Board (Device Tree)";
12 compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750";
13
14 aliases {
Jim Liuc7885742022-07-12 17:24:07 +0800[diff] [blame]15 eth0 = &emc0;
16 eth1 = &gmac0;
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]17 serial0 = &serial0;
18 serial1 = &serial1;
19 serial2 = &serial2;
20 serial3 = &serial3;
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
24 i2c3 = &i2c3;
25 i2c4 = &i2c4;
26 i2c5 = &i2c5;
27 i2c6 = &i2c6;
28 i2c7 = &i2c7;
29 i2c8 = &i2c8;
30 i2c9 = &i2c9;
31 i2c10 = &i2c10;
32 i2c11 = &i2c11;
33 i2c12 = &i2c12;
34 i2c13 = &i2c13;
35 i2c14 = &i2c14;
36 i2c15 = &i2c15;
Jim Liuc7885742022-07-12 17:24:07 +0800[diff] [blame]37 spi0 = &fiu0;
38 spi1 = &fiu3;
39 spi2 = &fiux;
40 spi3 = &spi0;
41 spi4 = &spi1;
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]42 };
43
44 chosen {
45 stdout-path = &serial0;
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0x0 0x20000000>;
51 };
52};
53
Jim Liuc7885742022-07-12 17:24:07 +0800[diff] [blame]54&udc0 {
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]55 status = "okay";
Jim Liuc7885742022-07-12 17:24:07 +0800[diff] [blame]56 phys = <&usbphy1 0>;
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]57};
58
Jim Liuc7885742022-07-12 17:24:07 +0800[diff] [blame]59&gmac0 {
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]60 phy-mode = "rgmii-id";
Jim Liuc7885742022-07-12 17:24:07 +0800[diff] [blame]61 snps,eee-force-disable;
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]62 status = "okay";
63};
64
65&ehci1 {
66 status = "okay";
Jim Liuc7885742022-07-12 17:24:07 +0800[diff] [blame]67 phys = <&usbphy2 3>;
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]68};
69
70&fiu0 {
71 status = "okay";
72 spi-nor@0 {
73 compatible = "jedec,spi-nor";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 spi-rx-bus-width = <2>;
77 reg = <0>;
78 spi-max-frequency = <5000000>;
79 partitions@80000000 {
80 compatible = "fixed-partitions";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 bbuboot1@0 {
84 label = "bb-uboot-1";
85 reg = <0x0000000 0x80000>;
86 read-only;
87 };
88 bbuboot2@80000 {
89 label = "bb-uboot-2";
90 reg = <0x0080000 0x80000>;
91 read-only;
92 };
93 envparam@100000 {
94 label = "env-param";
95 reg = <0x0100000 0x40000>;
96 read-only;
97 };
98 spare@140000 {
99 label = "spare";
100 reg = <0x0140000 0xC0000>;
101 };
102 kernel@200000 {
103 label = "kernel";
104 reg = <0x0200000 0x400000>;
105 };
106 rootfs@600000 {
107 label = "rootfs";
108 reg = <0x0600000 0x700000>;
109 };
110 spare1@d00000 {
111 label = "spare1";
112 reg = <0x0D00000 0x200000>;
113 };
114 spare2@f00000 {
115 label = "spare2";
116 reg = <0x0F00000 0x200000>;
117 };
118 spare3@1100000 {
119 label = "spare3";
120 reg = <0x1100000 0x200000>;
121 };
122 spare4@1300000 {
123 label = "spare4";
124 reg = <0x1300000 0x0>;
125 };
126 };
127 };
128};
129
130&fiu3 {
131 pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
132 status = "okay";
133 spi-nor@0 {
134 compatible = "jedec,spi-nor";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 spi-rx-bus-width = <2>;
138 reg = <0>;
139 spi-max-frequency = <5000000>;
140 partitions@A0000000 {
141 compatible = "fixed-partitions";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 system1@0 {
145 label = "spi3-system1";
146 reg = <0x0 0x0>;
147 };
148 };
149 };
150};
151
152&fiux {
153 spix-mode;
154};
155
Jim Liuc7885742022-07-12 17:24:07 +0800[diff] [blame]156&watchdog0 {
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]157 status = "okay";
158};
159
160&rng {
161 status = "okay";
162};
163
Jim Liuc7885742022-07-12 17:24:07 +0800[diff] [blame]164&sha {
165 status = "okay";
166};
167
168&aes {
169 status = "okay";
170};
171
Jim Liu4359b332022-04-19 13:32:19 +0800[diff] [blame]172&serial0 {
173 status = "okay";
174 clock-frequency = <24000000>;
175};
176
177&serial1 {
178 status = "okay";
179};
180
181&serial2 {
182 status = "okay";
183};
184
185&serial3 {
186 status = "okay";
187};
188
189&adc {
190 status = "okay";
191};
192
193&lpc_kcs {
194 kcs1: kcs1@0 {
195 status = "okay";
196 };
197
198 kcs2: kcs2@0 {
199 status = "okay";
200 };
201
202 kcs3: kcs3@0 {
203 status = "okay";
204 };
205};
206
207/* lm75 on SVB */
208&i2c0 {
209 clock-frequency = <100000>;
210 status = "okay";
211 lm75@48 {
212 compatible = "lm75";
213 reg = <0x48>;
214 status = "okay";
215 };
216};
217
218/* lm75 on EB */
219&i2c1 {
220 clock-frequency = <100000>;
221 status = "okay";
222 lm75@48 {
223 compatible = "lm75";
224 reg = <0x48>;
225 status = "okay";
226 };
227};
228
229/* tmp100 on EB */
230&i2c2 {
231 clock-frequency = <100000>;
232 status = "okay";
233 tmp100@48 {
234 compatible = "tmp100";
235 reg = <0x48>;
236 status = "okay";
237 };
238};
239
240&i2c3 {
241 clock-frequency = <100000>;
242 status = "okay";
243};
244
245&i2c5 {
246 clock-frequency = <100000>;
247 status = "okay";
248};
249
250/* tmp100 on SVB */
251&i2c6 {
252 clock-frequency = <100000>;
253 status = "okay";
254 tmp100@48 {
255 compatible = "tmp100";
256 reg = <0x48>;
257 status = "okay";
258 };
259};
260
261&i2c7 {
262 clock-frequency = <100000>;
263 status = "okay";
264};
265
266&i2c8 {
267 clock-frequency = <100000>;
268 status = "okay";
269};
270
271&i2c9 {
272 clock-frequency = <100000>;
273 status = "okay";
274};
275
276&i2c10 {
277 clock-frequency = <100000>;
278 status = "okay";
279};
280
281&i2c11 {
282 clock-frequency = <100000>;
283 status = "okay";
284};
285
286&i2c14 {
287 clock-frequency = <100000>;
288 status = "okay";
289};
290
291&pwm_fan {
292 status = "okay";
293 fan@0 {
294 reg = <0x00>;
295 fan-tach-ch = /bits/ 8 <0x00 0x01>;
296 cooling-levels = <127 255>;
297 };
298 fan@1 {
299 reg = <0x01>;
300 fan-tach-ch = /bits/ 8 <0x02 0x03>;
301 cooling-levels = /bits/ 8 <127 255>;
302 };
303 fan@2 {
304 reg = <0x02>;
305 fan-tach-ch = /bits/ 8 <0x04 0x05>;
306 cooling-levels = /bits/ 8 <127 255>;
307 };
308 fan@3 {
309 reg = <0x03>;
310 fan-tach-ch = /bits/ 8 <0x06 0x07>;
311 cooling-levels = /bits/ 8 <127 255>;
312 };
313 fan@4 {
314 reg = <0x04>;
315 fan-tach-ch = /bits/ 8 <0x08 0x09>;
316 cooling-levels = /bits/ 8 <127 255>;
317 };
318 fan@5 {
319 reg = <0x05>;
320 fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
321 cooling-levels = /bits/ 8 <127 255>;
322 };
323 fan@6 {
324 reg = <0x06>;
325 fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
326 cooling-levels = /bits/ 8 <127 255>;
327 };
328 fan@7 {
329 reg = <0x07>;
330 fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
331 cooling-levels = /bits/ 8 <127 255>;
332 };
333};
334
335&spi0 {
336 cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
337 status = "okay";
338 Flash@0 {
339 compatible = "winbond,w25q128",
340 "jedec,spi-nor";
341 reg = <0x0>;
342 #address-cells = <1>;
343 #size-cells = <1>;
344 spi-max-frequency = <5000000>;
345 partition@0 {
346 label = "spi0_spare1";
347 reg = <0x0000000 0x800000>;
348 };
349 partition@1 {
350 label = "spi0_spare2";
351 reg = <0x800000 0x0>;
352 };
353 };
354};
355
356&spi1 {
357 cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
358 status = "okay";
359 Flash@0 {
360 compatible = "winbond,w25q128fw",
361 "jedec,spi-nor";
362 reg = <0x0>;
363 #address-cells = <1>;
364 #size-cells = <1>;
365 spi-max-frequency = <5000000>;
366 partition@0 {
367 label = "spi1_spare1";
368 reg = <0x0000000 0x800000>;
369 };
370 partition@1 {
371 label = "spi1_spare2";
372 reg = <0x800000 0x0>;
373 };
374 };
375};
376
377&pinctrl {
378 pinctrl-names = "default";
379 pinctrl-0 = < &iox1_pins
380 &pin8_input
381 &pin9_output_high
382 &pin10_input
383 &pin11_output_high
384 &pin16_input
385 &pin24_output_high
386 &pin25_output_low
387 &pin32_output_high
388 &jtag2_pins
389 &pin61_output_high
390 &pin62_output_high
391 &pin63_output_high
392 &lpc_pins
393 &pin160_input
394 &pin162_input
395 &pin168_input
396 &pin169_input
397 &pin170_input
398 &pin187_output_high
399 &pin190_input
400 &pin191_output_high
401 &pin192_output_high
402 &pin197_output_low
403 &ddc_pins
404 &pin218_input
405 &pin219_output_low
406 &pin220_output_low
407 &pin221_output_high
408 &pin222_input
409 &pin223_output_low
410 &spix_pins
411 &pin228_output_low
412 &pin231_output_high
413 &pin255_input>;
414};
415
Jim Liuc7885742022-07-12 17:24:07 +0800[diff] [blame]416&ehci1 {
417 status = "okay";
418 phys = <&usbphy2 3>;
419};
420
421&otp {
422 status = "okay";
423};
424
425&usbphy1 {
426 status = "okay";
427};
428
429&usbphy2 {
430 status = "okay";
431};
432
433&emc0 {
434 status = "okay";
435 pinctrl-names = "default";
436 pinctrl-0 = <&r1_pins
437 &r1err_pins>;
438 fixed-link {
439 speed = <100>;
440 full-dulpex;
441 };
442};
443
444&sdhci0 {
445 status = "okay";
446};