blob: 48f9320e7ae590bb02234598f0e321233bcb34fa [file] [log] [blame]
developer56ed64c2022-09-09 19:59:13 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7986.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "mt7986-rfb";
15 compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
16 "mediatek,mt7986-sd-rfb";
17 chosen {
18 stdout-path = &uart0;
19 tick-timer = &timer0;
20 };
21
22 reg_3p3v: regulator-3p3v {
23 compatible = "regulator-fixed";
24 regulator-name = "fixed-3.3V";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 regulator-boot-on;
28 regulator-always-on;
29 };
30};
31
32&uart0 {
33 status = "okay";
34};
35
36&uart1 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&uart1_pins>;
39 status = "disabled";
40};
41
42&eth {
43 status = "okay";
44 mediatek,gmac-id = <0>;
45 phy-mode = "sgmii";
46 mediatek,switch = "mt7531";
47 reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
48
49 fixed-link {
50 speed = <1000>;
51 full-duplex;
52 };
53};
54
55&pinctrl {
56 spi_flash_pins: spi0-pins-func-1 {
57 mux {
58 function = "flash";
59 groups = "spi0", "spi0_wp_hold";
60 };
61
62 conf-pu {
63 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
64 drive-strength = <MTK_DRIVE_8mA>;
65 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
66 };
67
68 conf-pd {
69 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
70 drive-strength = <MTK_DRIVE_8mA>;
71 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
72 };
73 };
74
75 spic_pins: spi1-pins-func-1 {
76 mux {
77 function = "spi";
78 groups = "spi1_2";
79 };
80 };
81
82 uart1_pins: spi1-pins-func-3 {
83 mux {
84 function = "uart";
85 groups = "uart1_2";
86 };
87 };
88
89 pwm_pins: pwm0-pins-func-1 {
90 mux {
91 function = "pwm";
92 groups = "pwm0";
93 };
94 };
95
96 mmc0_pins_default: mmc0default {
97 mux {
98 function = "flash";
99 groups = "emmc_45";
100 input-schmitt-enable;
101 };
102
103 conf-cmd-dat {
104 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
105 "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
106 "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
107 input-enable;
108 drive-strength = <MTK_DRIVE_4mA>;
109 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
110 };
111
112 conf-clk {
113 pins = "SPI1_CS";
114 drive-strength = <MTK_DRIVE_6mA>;
115 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
116 };
117
118 conf-rst {
119 pins = "PWM1";
120 drive-strength = <MTK_DRIVE_4mA>;
121 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
122 };
123 };
124};
125
126&spi0 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&spi_flash_pins>;
131 status = "okay";
132 must_tx;
133 enhance_timing;
134 dma_ext;
135 ipm_design;
136 support_quad;
137 tick_dly = <2>;
138 sample_sel = <0>;
139
140 spi_nor@0 {
141 compatible = "jedec,spi-nor";
142 reg = <0>;
143 spi-max-frequency = <52000000>;
144 };
145
146 spi_nand@1 {
147 compatible = "spi-nand";
148 reg = <1>;
149 spi-max-frequency = <52000000>;
150 };
151};
152
153&pwm {
154 pinctrl-names = "default";
155 pinctrl-0 = <&pwm_pins>;
156 status = "okay";
157};
158
159&watchdog {
160 status = "disabled";
161};
162
163&mmc0 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&mmc0_pins_default>;
166 bus-width = <4>;
167 max-frequency = <52000000>;
168 cap-sd-highspeed;
169 r_smpl = <1>;
170 vmmc-supply = <&reg_3p3v>;
171 vqmmc-supply = <&reg_3p3v>;
172 status = "okay";
173};