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Bernhard Messerklingerd9461aa2020-05-18 12:33:34 +02001* Intel FSP-M configuration
2
3Several Intel platforms require the execution of the Intel FSP (Firmware
4Support Package) for initialization. The FSP consists of multiple parts, one
5of which is the FSP-M (Memory initialization phase).
6
7This binding applies to the FSP-M for the Intel Apollo Lake SoC.
8
9The FSP-M is available on Github [1].
10For detailed information on the FSP-M parameters see the documentation in
11FSP/ApolloLakeFspBinPkg/Docs [2].
12
13The properties of this binding are all optional. If no properties are set the
14values of the FSP-M are used.
15
16[1] https://github.com/IntelFsp/FSP
17[2] https://github.com/IntelFsp/FSP/tree/master/ApolloLakeFspBinPkg/Docs
18
19Optional properties:
20- fspm,serial-debug-port-address: Debug Serial Port Base address
21- fspm,serial-debug-port-type: Debug Serial Port Type
22 0: NONE
23 1: I/O
24 2: MMIO (default)
25- fspm,serial-debug-port-device: Serial Port Debug Device
26 0: SOC UART0
27 1: SOC UART1
28 2: SOC UART2 (default)
29 3: External Device
30- fspm,serial-debug-port-stride-size: Debug Serial Port Stride Size
31 0: 1
32 2: 4 (default)
33- fspm,mrc-fast-boot: Memory Fast Boot
34- fspm,igd: Integrated Graphics Device
35- fspm,igd-dvmt50-pre-alloc: DVMT Pre-Allocated
36 0x02: 64 MB (default)
37 0x03: 96 MB
38 0x04: 128 MB
39 0x05: 160 MB
40 0x06: 192 MB
41 0x07: 224 MB
42 0x08: 256 MB
43 0x09: 288 MB
44 0x0A: 320 MB
45 0x0B: 352 MB
46 0x0C: 384 MB
47 0x0D: 416 MB
48 0x0E: 448 MB
49 0x0F: 480 MB
50 0x10: 512 MB
51- fspm,aperture-size: Aperture Size
52 0x1: 128 MB (default)
53 0x2: 256 MB
54 0x3: 512 MB
55- fspm,gtt-size: GTT Size
56 0x1: 2 MB
57 0x2: 4 MB
58 0x3: 8 MB (default)
59- fspm,primary-video-adaptor: Primary Display
60 0x0: AUTO (default)
61 0x2: IGD
62 0x3: PCI
63- fspm,package: Package
64 0x0: SODIMM (default)
65 0x1: BGA
66 0x2: BGA mirrored (LPDDR3 only)
67 0x3: SODIMM/UDIMM with Rank 1 Mirrored (DDR3L)
68- fspm,profile: Profile
69 0x01: WIO2_800_7_8_8
70 0x02: WIO2_1066_9_10_10
71 0x03: LPDDR3_1066_8_10_10
72 0x04: LPDDR3_1333_10_12_12
73 0x05: LPDDR3_1600_12_15_15
74 0x06: LPDDR3_1866_14_17_17
75 0x07: LPDDR3_2133_16_20_20
76 0x08: LPDDR4_1066_10_10_10
77 0x09: LPDDR4_1600_14_15_15
78 0x0A: LPDDR4_2133_20_20_20
79 0x0B: LPDDR4_2400_24_22_22
80 0x0C: LPDDR4_2666_24_24_24
81 0x0D: LPDDR4_2933_28_27_27
82 0x0E: LPDDR4_3200_28_29_29
83 0x0F: DDR3_1066_6_6_6
84 0x10: DDR3_1066_7_7_7
85 0x11: DDR3_1066_8_8_8
86 0x12: DDR3_1333_7_7_7
87 0x13: DDR3_1333_8_8_8
88 0x14: DDR3_1333_9_9_9
89 0x15: DDR3_1333_10_10_10
90 0x16: DDR3_1600_8_8_8
91 0x17: DDR3_1600_9_9_9
92 0x18: DDR3_1600_10_10_10
93 0x19: DDR3_1600_11_11_11 (default)
94 0x1A: DDR3_1866_10_10_10
95 0x1B: DDR3_1866_11_11_11
96 0x1C: DDR3_1866_12_12_12
97 0x1D: DDR3_1866_13_13_13
98 0x1E: DDR3_2133_11_11_11
99 0x1F: DDR3_2133_12_12_12
100 0x20: DDR3_2133_13_13_13
101 0x21: DDR3_2133_14_14_14
102 0x22: DDR4_1333_10_10_10
103 0x23: DDR4_1600_10_10_10
104 0x24: DDR4_1600_11_11_11
105 0x25: DDR4_1600_12_12_12
106 0x26: DDR4_1866_12_12_12
107 0x27: DDR4_1866_13_13_13
108 0x28: DDR4_1866_14_14_14
109 0x29: DDR4_2133_14_14_14
110 0x2A: DDR4_2133_15_15_15
111 0x2B: DDR4_2133_16_16_16
112 0x2C: DDR4_2400_15_15_15
113 0x2D: DDR4_2400_16_16_16
114 0x2E: DDR4_2400_17_17_17
115 0x2F: DDR4_2400_18_18_18
116- fspm,memory-down: Memory Down
117 0x0: No (default)
118 0x1: Yes
119 0x2: 1MD+SODIMM (for DDR3L only) ACRD
120 0x3: 1x32 LPDDR4
121- fspm,ddr3l-page-size: DDR3LPageSize
122 0x1: 1KB (default)
123 0x2: 2KB
124- fspm,ddr3-lasr: DDR3LASR
125- fspm,scrambler-support: ScramblerSupport
126- fspm,interleaved-mode: InterleavedMode
127- fspm,channel-hash-mask: ChannelHashMask
128- fspm,fspm,slice-hash-mask: SliceHashMask
129- fspm,channels-slices-enable: ChannelsSlices
130- fspm,min-ref-rate2x-enable: MinRefRate2x
131- fspm,dual-rank-support-enable: DualRankSupport
132- fspm,rmt-mode: RmtMode
133- fspm,memory-size-limit: MemorySizeLimit
134- fspm,low-memory-max-value: LowMemoryMaxValue
135- fspm,high-memory-max-value: HighMemoryMaxValue
136- fspm,disable-fast-boot: FastBoot
137- fspm,dimm0-spd-address: DIMM0 SPD Address
138- fspm,dimm1-spd-address: DIMM1 SPD Address
139- fspm,chX-rank-enable: Must be set to enable rank (X = 0-3)
140- fspm,chX-device-width: DRAM device width per DRAM channel (X = 0-3)
141 0: x8
142 1: x16
143 2: x32
144 3: x64
145- fspm,chX-dram-density: Must specify the DRAM device density (X = 0-3)
146 0: 4Gb
147 1: 6Gb
148 2: 8Gb
149 3: 12Gb
150 4: 16Gb
151 5: 2Gb
152- fspm,chX-option: Channel options (X = 0-3)
153- fspm,chX-odt-config: Channel Odt Config (X = 0-3)
154- fspm,chX-mode2-n: Force 2N Mode (X = 0-3)
155 0x0: Auto
156 0x1: Force 2N CMD Timing Mode
157- fspm,chX-odt-levels: Channel Odt Levels (X = 0-3)
158 0: ODT Connected to SoC
159 1: ODT held high
160- fspm,rmt-check-run: RmtCheckRun
161- fspm,rmt-margin-check-scale-high-threshold: RmtMarginCheckScaleHighThreshold
162- fspm,ch-bit-swizzling: Bit_swizzling
163- fspm,msg-level-mask: MsgLevelMask
164- fspm,pre-mem-gpio-table-pin-num: PreMem GPIO Pin Number for each table
165- fspm,pre-mem-gpio-table-ptr: PreMem GPIO Table Pointer
166- fspm,pre-mem-gpio-table-entry-num: PreMem GPIO Table Entry Number
167- fspm,enhance-port8xh-decoding: Enhance the port 8xh decoding
168- fspm,spd-write-enable: SPD Data Write
169- fspm,mrc-data-saving: MRC Training Data Saving
170- fspm,oem-loading-base: OEM File Loading Address
171- fspm,oem-file-name: OEM File Name to Load
172- fspm,mrc-boot-data-ptr:
173- fspm,e-mmc-trace-len: eMMC Trace Length
174 0x0: Long
175 0x1: Short
176- fspm,skip-cse-rbp: Skip CSE RBP to support zero sized IBB
177- fspm,npk-en: Npk Enable
178 0: Disable
179 1: Enable
180 2: Debugger
181 3: Auto (default)
182- fspm,fw-trace-en: FW Trace Enable
183- fspm,fw-trace-destination: FW Trace Destination
184 1: NPK_TRACE_TO_MEMORY
185 2: NPK_TRACE_TO_DCI
186 3: NPK_TRACE_TO_BSSB
187 4: NPK_TRACE_TO_PTI (default)
188- fspm,recover-dump: NPK Recovery Dump
189- fspm,msc0-wrap: Memory Region 0 Buffer WrapAround
190 0: n0-warp
191 1: n1-warp (default)
192- fspm,msc1-wrap: Memory Region 1 Buffer WrapAround
193 0: n0-warp
194 1: n1-warp (default)
195- fspm,msc0-size: Memory Region 0 Buffer Size
196 0: 0MB (default)
197 1: 1MB
198 2: 8MB
199 3: 64MB
200 4: 128MB
201 5: 256MB
202 6: 512MB
203 7: 1GB
204- fspm,msc1-size: Memory Region 1 Buffer Size
205 0: 0MB (default)
206 1: 1MB
207 2: 8MB
208 3: 64MB
209 4: 128MB
210 5: 256MB
211 6: 512MB
212 7: 1GB
213- fspm,pti-mode: PTI Mode
214 0: 0ff
215 1: x4 (default)
216 2: x8
217 3: x12
218 4: x16
219- fspm,pti-training: PTI Training
220 0: off (default)
221 1-6: 1-6
222- fspm,pti-speed:
223 0: full
224 1: half
225 2: quarter (default)
226- fspm,punit-mlvl: Punit Message Level
227 0:
228 1: (default)
229 2-4: 2-4
230- fspm,pmc-mlvl: PMC Message Level
231 0:
232 1: (default)
233 2-4: 2-4
234- fspm,sw-trace-en: SW Trace Enable
235- fspm,periodic-retraining-disable: Periodic Retraining Disable
236- fspm,enable-reset-system: Enable Reset System
237- fspm,enable-s3-heci2: Enable HECI2 in S3 resume path
238- fspm,variable-nvs-buffer-ptr:
239
240Example:
241
242&host_bridge {
243 fspm,package = <PACKAGE_BGA>;
244 fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>;
245 fspm,memory-down = <MEMORY_DOWN_YES>;
246 fspm,scrambler-support = <1>;
247 fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>;
248 fspm,channel-hash-mask = <0x36>;
249 fspm,slice-hash-mask = <0x9>;
250 fspm,low-memory-max-value = <2048>;
251 fspm,ch0-rank-enable = <1>;
252 fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>;
253 fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>;
254 fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING |
255 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
256 fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
257 fspm,ch1-rank-enable = <1>;
258 fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>;
259 fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>;
260 fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING |
261 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
262 fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
263 fspm,ch2-rank-enable = <1>;
264 fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>;
265 fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>;
266 fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING |
267 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
268 fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
269 fspm,ch3-rank-enable = <1>;
270 fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>;
271 fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>;
272 fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING |
273 CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
274 fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
275 fspm,fspm,skip-cse-rbp = <1>;
276
277 fspm,ch-bit-swizzling = /bits/ 8 <
278 /* LP4_PHYS_CH0A */
279
280 /* DQA[0:7] pins of LPDDR4 module */
281 6 7 5 4 3 1 0 2
282 /* DQA[8:15] pins of LPDDR4 module */
283 12 10 11 13 14 8 9 15
284 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
285 16 22 23 20 18 17 19 21
286 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
287 30 28 29 25 24 26 27 31
288
289 /* LP4_PHYS_CH0B */
290 /* DQA[0:7] pins of LPDDR4 module */
291 7 3 5 2 6 0 1 4
292 /* DQA[8:15] pins of LPDDR4 module */
293 9 14 12 13 10 11 8 15
294 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
295 20 22 23 16 19 17 18 21
296 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
297 28 24 26 27 29 30 31 25
298
299 /* LP4_PHYS_CH1A */
300
301 /* DQA[0:7] pins of LPDDR4 module */
302 2 1 6 7 5 4 3 0
303 /* DQA[8:15] pins of LPDDR4 module */
304 11 10 8 9 12 15 13 14
305 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
306 17 23 19 16 21 22 20 18
307 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
308 31 29 26 25 28 27 24 30
309
310 /* LP4_PHYS_CH1B */
311
312 /* DQA[0:7] pins of LPDDR4 module */
313 4 3 7 5 6 1 0 2
314 /* DQA[8:15] pins of LPDDR4 module */
315 15 9 8 11 14 13 12 10
316 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
317 20 23 22 21 18 19 16 17
318 /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
319 25 28 30 31 26 27 24 29>;
320};