| Sumit Garg | e6a488b | 2022-07-12 12:42:11 +0530 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Qualcomm QCS404 sysmap |
| 4 | * |
| 5 | * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org> |
| 6 | */ |
| 7 | #ifndef _MACH_SYSMAP_QCS404_H |
| 8 | #define _MACH_SYSMAP_QCS404_H |
| 9 | |
| 10 | #define GICD_BASE (0x0b000000) |
| 11 | #define GICC_BASE (0x0b002000) |
| 12 | |
| 13 | /* Clocks: (from CLK_CTL_BASE) */ |
| 14 | #define GPLL0_STATUS (0x21000) |
| 15 | #define APCS_GPLL_ENA_VOTE (0x45000) |
| 16 | #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) |
| 17 | |
| 18 | /* BLSP1 AHB clock (root clock for BLSP) */ |
| 19 | #define BLSP1_AHB_CBCR 0x1008 |
| 20 | |
| 21 | /* Uart clock control registers */ |
| 22 | #define BLSP1_UART2_BCR (0x3028) |
| 23 | #define BLSP1_UART2_APPS_CBCR (0x302C) |
| 24 | #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) |
| 25 | #define BLSP1_UART2_APPS_CFG_RCGR (0x3038) |
| 26 | #define BLSP1_UART2_APPS_M (0x303C) |
| 27 | #define BLSP1_UART2_APPS_N (0x3040) |
| 28 | #define BLSP1_UART2_APPS_D (0x3044) |
| 29 | |
| 30 | /* SD controller clock control registers */ |
| 31 | #define SDCC_BCR(n) (((n) * 0x1000) + 0x41000) |
| 32 | #define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004) |
| 33 | #define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008) |
| 34 | #define SDCC_M(n) (((n) * 0x1000) + 0x4100C) |
| 35 | #define SDCC_N(n) (((n) * 0x1000) + 0x41010) |
| 36 | #define SDCC_D(n) (((n) * 0x1000) + 0x41014) |
| 37 | #define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018) |
| 38 | #define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C) |
| 39 | |
| 40 | #endif |