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Bo Shen06ce3f42014-02-09 15:52:39 +08001/*
2 * Configuration settings for the SAMA5D3 Xplained board.
3 *
4 * Copyright (C) 2014 Atmel Corporation
5 * Bo Shen <voice.shen@atmel.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include <asm/hardware.h>
14
15#define CONFIG_SYS_TEXT_BASE 0x26f00000
16
17/* ARM asynchronous clock */
18#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
19#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
Bo Shen06ce3f42014-02-09 15:52:39 +080020
21#define CONFIG_AT91FAMILY
22#define CONFIG_ARCH_CPU_INIT
Bo Shen735ef1a2014-03-19 14:48:45 +080023
24#ifndef CONFIG_SPL_BUILD
Bo Shen06ce3f42014-02-09 15:52:39 +080025#define CONFIG_SKIP_LOWLEVEL_INIT
Bo Shen735ef1a2014-03-19 14:48:45 +080026#endif
27
Bo Shen06ce3f42014-02-09 15:52:39 +080028#define CONFIG_BOARD_EARLY_INIT_F
29#define CONFIG_DISPLAY_CPUINFO
30
31#define CONFIG_CMD_BOOTZ
32#define CONFIG_OF_LIBFDT /* Device Tree support */
33
Bo Shene69bb892014-04-24 11:42:14 +080034#define CONFIG_SYS_GENERIC_BOARD
35
Bo Shen06ce3f42014-02-09 15:52:39 +080036/* general purpose I/O */
37#define CONFIG_AT91_GPIO
38
39/* serial console */
40#define CONFIG_ATMEL_USART
41#define CONFIG_USART_BASE ATMEL_BASE_DBGU
42#define CONFIG_USART_ID ATMEL_ID_DBGU
43
44/*
45 * This needs to be defined for the OHCI code to work but it is defined as
46 * ATMEL_ID_UHPHS in the CPU specific header files.
47 */
48#define ATMEL_ID_UHP ATMEL_ID_UHPHS
49
50/*
51 * Specify the clock enable bit in the PMC_SCER register.
52 */
53#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
54
55#define CONFIG_BOOTDELAY 3
56
57/*
58 * BOOTP options
59 */
60#define CONFIG_BOOTP_BOOTFILESIZE
61#define CONFIG_BOOTP_BOOTPATH
62#define CONFIG_BOOTP_GATEWAY
63#define CONFIG_BOOTP_HOSTNAME
64
65/* No NOR flash */
66#define CONFIG_SYS_NO_FLASH
67
68/*
69 * Command line configuration.
70 */
71#include <config_cmd_default.h>
72#undef CONFIG_CMD_FPGA
73#undef CONFIG_CMD_IMI
74#undef CONFIG_CMD_LOADS
75#define CONFIG_CMD_PING
76#define CONFIG_CMD_DHCP
77
78/* SDRAM */
79#define CONFIG_NR_DRAM_BANKS 1
80#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
81#define CONFIG_SYS_SDRAM_SIZE 0x10000000
82
Bo Shen735ef1a2014-03-19 14:48:45 +080083#ifdef CONFIG_SPL_BUILD
84#define CONFIG_SYS_INIT_SP_ADDR 0x310000
85#else
Bo Shen06ce3f42014-02-09 15:52:39 +080086#define CONFIG_SYS_INIT_SP_ADDR \
87 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shen735ef1a2014-03-19 14:48:45 +080088#endif
Bo Shen06ce3f42014-02-09 15:52:39 +080089
90/* NAND flash */
91#define CONFIG_CMD_NAND
92
93#ifdef CONFIG_CMD_NAND
94#define CONFIG_NAND_ATMEL
95#define CONFIG_SYS_MAX_NAND_DEVICE 1
96#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
97/* our ALE is AD21 */
98#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
99/* our CLE is AD22 */
100#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
101#define CONFIG_SYS_NAND_ONFI_DETECTION
102/* PMECC & PMERRLOC */
103#define CONFIG_ATMEL_NAND_HWECC
104#define CONFIG_ATMEL_NAND_HW_PMECC
105#define CONFIG_PMECC_CAP 4
106#define CONFIG_PMECC_SECTOR_SIZE 512
107#define CONFIG_CMD_NAND_TRIMFFS
108#define CONFIG_CMD_MTDPARTS
109
110#define CONFIG_MTD_DEVICE
111#define CONFIG_MTD_PARTITIONS
112#define CONFIG_RBTREE
113#define CONFIG_LZO
114#define CONFIG_CMD_UBI
115#define CONFIG_CMD_UBIFS
116#endif
117
118/* Ethernet Hardware */
119#define CONFIG_MACB
120#define CONFIG_RMII
121#define CONFIG_NET_MULTI
122#define CONFIG_NET_RETRY_COUNT 20
123#define CONFIG_MACB_SEARCH_PHY
124#define CONFIG_RGMII
125#define CONFIG_CMD_MII
126#define CONFIG_PHYLIB
127
128/* MMC */
129#define CONFIG_CMD_MMC
130
131#ifdef CONFIG_CMD_MMC
132#define CONFIG_MMC
133#define CONFIG_GENERIC_MMC
134#define CONFIG_GENERIC_ATMEL_MCI
135#define CONFIG_ATMEL_MCI_8BIT
136#endif
137
138/* USB */
139#define CONFIG_CMD_USB
140
141#ifdef CONFIG_CMD_USB
142#define CONFIG_USB_ATMEL
143#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
144#define CONFIG_USB_OHCI_NEW
145#define CONFIG_SYS_USB_OHCI_CPU_INIT
146#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
147#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
148#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
149#define CONFIG_DOS_PARTITION
150#define CONFIG_USB_STORAGE
151#endif
152
153#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
154#define CONFIG_CMD_FAT
155#define CONFIG_FAT_WRITE
156#define CONFIG_CMD_EXT4
157#define CONFIG_CMD_EXT4_WRITE
158#endif
159
160#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
161
162#if CONFIG_SYS_USE_NANDFLASH
163/* bootstrap + u-boot + env in nandflash */
164#define CONFIG_ENV_IS_IN_NAND
165#define CONFIG_ENV_OFFSET 0xc0000
166#define CONFIG_ENV_OFFSET_REDUND 0x100000
167#define CONFIG_ENV_SIZE 0x20000
168#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \
169 "nand read 0x22000000 0x200000 0x600000;" \
170 "bootz 0x22000000 - 0x21000000"
171#elif CONFIG_SYS_USE_MMC
172/* bootstrap + u-boot + env in sd card */
173#define CONFIG_ENV_IS_IN_MMC
174#define CONFIG_ENV_OFFSET 0x2000
175#define CONFIG_ENV_SIZE 0x1000
176#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \
177 "fatload mmc 0:1 0x22000000 zImage; " \
178 "bootz 0x22000000 - 0x21000000"
179#define CONFIG_SYS_MMC_ENV_DEV 0
180#else
181#define CONFIG_ENV_IS_NOWHERE
182#endif
183
184#ifdef CONFIG_SYS_USE_MMC
185#define CONFIG_BOOTARGS \
186 "console=ttyS0,115200 earlyprintk " \
187 "root=/dev/mmcblk0p2 rw rootwait"
188#else
189#define CONFIG_BOOTARGS \
190 "console=ttyS0,115200 earlyprintk " \
191 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
192 "256K(env),256k(evn_redundent),256k(spare)," \
193 "512k(dtb),6M(kernel)ro,-(rootfs) " \
194 "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
195#endif
196
197#define CONFIG_BAUDRATE 115200
198
199#define CONFIG_SYS_PROMPT "U-Boot> "
200#define CONFIG_SYS_CBSIZE 256
201#define CONFIG_SYS_MAXARGS 16
202#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
203 sizeof(CONFIG_SYS_PROMPT) + 16)
204#define CONFIG_SYS_LONGHELP
205#define CONFIG_CMDLINE_EDITING
206#define CONFIG_AUTO_COMPLETE
207#define CONFIG_SYS_HUSH_PARSER
208
209/* Size of malloc() pool */
210#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
211
Bo Shen735ef1a2014-03-19 14:48:45 +0800212/* SPL */
213#define CONFIG_SPL
214#define CONFIG_SPL_FRAMEWORK
215#define CONFIG_SPL_TEXT_BASE 0x300000
216#define CONFIG_SPL_MAX_SIZE 0x10000
217#define CONFIG_SPL_BSS_START_ADDR 0x20000000
218#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
219#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
220#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
221
222#define CONFIG_SPL_LIBCOMMON_SUPPORT
223#define CONFIG_SPL_LIBGENERIC_SUPPORT
224#define CONFIG_SPL_GPIO_SUPPORT
225#define CONFIG_SPL_SERIAL_SUPPORT
226
227#define CONFIG_SPL_BOARD_INIT
228#define CONFIG_SYS_MONITOR_LEN (512 << 10)
229
230#ifdef CONFIG_SYS_USE_MMC
231#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds
232#define CONFIG_SPL_MMC_SUPPORT
233#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
234#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
235#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
236#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
237#define CONFIG_SPL_FAT_SUPPORT
238#define CONFIG_SPL_LIBDISK_SUPPORT
239
240#elif CONFIG_SYS_USE_NANDFLASH
241#define CONFIG_SPL_NAND_SUPPORT
242#define CONFIG_SPL_NAND_DRIVERS
243#define CONFIG_SPL_NAND_BASE
244#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
245#define CONFIG_SYS_NAND_5_ADDR_CYCLE
246#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
247#define CONFIG_SYS_NAND_PAGE_COUNT 64
248#define CONFIG_SYS_NAND_OOBSIZE 64
249#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
250#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
251
252#endif
253
Bo Shen06ce3f42014-02-09 15:52:39 +0800254#endif