Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Stefan Roese <sr@denx.de> |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <dm.h> |
Simon Glass | 8e16b1e | 2019-12-28 10:45:05 -0700 | [diff] [blame] | 8 | #include <init.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 9 | #include <malloc.h> |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 10 | #include <ram.h> |
Stefan Roese | 81382b7 | 2018-10-09 08:59:10 +0200 | [diff] [blame] | 11 | #include <wdt.h> |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 12 | #include <asm/io.h> |
| 13 | #include <linux/io.h> |
| 14 | #include <linux/sizes.h> |
| 15 | #include "mt76xx.h" |
| 16 | |
| 17 | #define STR_LEN 6 |
| 18 | |
| 19 | #ifdef CONFIG_BOOT_ROM |
| 20 | int mach_cpu_init(void) |
| 21 | { |
| 22 | ddr_calibrate(); |
| 23 | |
| 24 | return 0; |
| 25 | } |
| 26 | #endif |
| 27 | |
| 28 | int dram_init(void) |
| 29 | { |
| 30 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M); |
| 31 | |
| 32 | return 0; |
| 33 | } |
| 34 | |
| 35 | int print_cpuinfo(void) |
| 36 | { |
| 37 | static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)", |
| 38 | "PLL (4-Byte SPI Addr)", |
| 39 | "XTAL (3-Byte SPI Addr)", |
| 40 | "XTAL (4-Byte SPI Addr)" }; |
| 41 | const void *blob = gd->fdt_blob; |
| 42 | void __iomem *sysc_base; |
| 43 | char buf[STR_LEN + 1]; |
| 44 | fdt_addr_t base; |
| 45 | fdt_size_t size; |
| 46 | char *str; |
| 47 | int node; |
| 48 | u32 val; |
| 49 | |
| 50 | /* Get system controller base address */ |
| 51 | node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc"); |
| 52 | if (node < 0) |
| 53 | return -FDT_ERR_NOTFOUND; |
| 54 | |
| 55 | base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg", |
| 56 | 0, &size, true); |
| 57 | if (base == FDT_ADDR_T_NONE) |
| 58 | return -EINVAL; |
| 59 | |
| 60 | sysc_base = ioremap_nocache(base, size); |
| 61 | |
| 62 | str = (char *)sysc_base + MT76XX_CHIPID_OFFS; |
| 63 | snprintf(buf, STR_LEN + 1, "%s", str); |
| 64 | val = readl(sysc_base + MT76XX_CHIP_REV_ID_OFFS); |
| 65 | printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf, |
| 66 | (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0)); |
| 67 | |
| 68 | val = (readl(sysc_base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1; |
| 69 | printf("Boot from %s\n", boot_str[val]); |
| 70 | |
| 71 | return 0; |
| 72 | } |
Stefan Roese | 17679e4 | 2019-05-28 08:11:37 +0200 | [diff] [blame] | 73 | |
| 74 | int last_stage_init(void) |
| 75 | { |
| 76 | void *src, *dst; |
| 77 | |
| 78 | src = malloc(SZ_64K); |
| 79 | dst = malloc(SZ_64K); |
| 80 | if (!src || !dst) { |
| 81 | printf("Can't allocate buffer for cache cleanup copy!\n"); |
| 82 | return 0; |
| 83 | } |
| 84 | |
| 85 | /* |
| 86 | * It has been noticed, that sometimes the d-cache is not in a |
| 87 | * "clean-state" when U-Boot is running on MT7688. This was |
| 88 | * detected when using the ethernet driver (which uses d-cache) |
| 89 | * and a TFTP command does not complete. Copying an area of 64KiB |
| 90 | * in DDR at a very late bootup time in U-Boot, directly before |
| 91 | * calling into the prompt, seems to fix this issue. |
| 92 | */ |
| 93 | memcpy(dst, src, SZ_64K); |
| 94 | free(src); |
| 95 | free(dst); |
| 96 | |
| 97 | return 0; |
| 98 | } |