blob: 39c25671d6743b41c9eb7f088ff5da176e0afd6b [file] [log] [blame]
Peng Fan75c84a62016-12-11 19:24:36 +08001/*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
11#define __DT_BINDINGS_CLOCK_IMX6SLL_H
12
13#define IMX6SLL_CLK_DUMMY 0
14#define IMX6SLL_CLK_CKIL 1
15#define IMX6SLL_CLK_OSC 2
16#define IMX6SLL_PLL1_BYPASS_SRC 3
17#define IMX6SLL_PLL2_BYPASS_SRC 4
18#define IMX6SLL_PLL3_BYPASS_SRC 5
19#define IMX6SLL_PLL4_BYPASS_SRC 6
20#define IMX6SLL_PLL5_BYPASS_SRC 7
21#define IMX6SLL_PLL6_BYPASS_SRC 8
22#define IMX6SLL_PLL7_BYPASS_SRC 9
23#define IMX6SLL_CLK_PLL1 10
24#define IMX6SLL_CLK_PLL2 11
25#define IMX6SLL_CLK_PLL3 12
26#define IMX6SLL_CLK_PLL4 13
27#define IMX6SLL_CLK_PLL5 14
28#define IMX6SLL_CLK_PLL6 15
29#define IMX6SLL_CLK_PLL7 16
30#define IMX6SLL_PLL1_BYPASS 17
31#define IMX6SLL_PLL2_BYPASS 18
32#define IMX6SLL_PLL3_BYPASS 19
33#define IMX6SLL_PLL4_BYPASS 20
34#define IMX6SLL_PLL5_BYPASS 21
35#define IMX6SLL_PLL6_BYPASS 22
36#define IMX6SLL_PLL7_BYPASS 23
37#define IMX6SLL_CLK_PLL1_SYS 24
38#define IMX6SLL_CLK_PLL2_BUS 25
39#define IMX6SLL_CLK_PLL3_USB_OTG 26
40#define IMX6SLL_CLK_PLL4_AUDIO 27
41#define IMX6SLL_CLK_PLL5_VIDEO 28
42#define IMX6SLL_CLK_PLL6_ENET 29
43#define IMX6SLL_CLK_PLL7_USB_HOST 30
44#define IMX6SLL_CLK_USBPHY1 31
45#define IMX6SLL_CLK_USBPHY2 32
46#define IMX6SLL_CLK_USBPHY1_GATE 33
47#define IMX6SLL_CLK_USBPHY2_GATE 34
48#define IMX6SLL_CLK_PLL2_PFD0 35
49#define IMX6SLL_CLK_PLL2_PFD1 36
50#define IMX6SLL_CLK_PLL2_PFD2 37
51#define IMX6SLL_CLK_PLL2_PFD3 38
52#define IMX6SLL_CLK_PLL3_PFD0 39
53#define IMX6SLL_CLK_PLL3_PFD1 40
54#define IMX6SLL_CLK_PLL3_PFD2 41
55#define IMX6SLL_CLK_PLL3_PFD3 42
56#define IMX6SLL_CLK_PLL4_POST_DIV 43
57#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44
58#define IMX6SLL_CLK_PLL5_POST_DIV 45
59#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46
60#define IMX6SLL_CLK_PLL2_198M 47
61#define IMX6SLL_CLK_PLL3_120M 48
62#define IMX6SLL_CLK_PLL3_80M 49
63#define IMX6SLL_CLK_PLL3_60M 50
64#define IMX6SLL_CLK_STEP 51
65#define IMX6SLL_CLK_PLL1_SW 52
66#define IMX6SLL_CLK_AXI_ALT_SEL 53
67#define IMX6SLL_CLK_AXI_SEL 54
68#define IMX6SLL_CLK_PERIPH_PRE 55
69#define IMX6SLL_CLK_PERIPH2_PRE 56
70#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57
71#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58
72#define IMX6SLL_CLK_PERCLK_SEL 59
73#define IMX6SLL_CLK_USDHC1_SEL 60
74#define IMX6SLL_CLK_USDHC2_SEL 61
75#define IMX6SLL_CLK_USDHC3_SEL 62
76#define IMX6SLL_CLK_SSI1_SEL 63
77#define IMX6SLL_CLK_SSI2_SEL 64
78#define IMX6SLL_CLK_SSI3_SEL 65
79#define IMX6SLL_CLK_PXP_SEL 66
80#define IMX6SLL_CLK_LCDIF_PRE_SEL 67
81#define IMX6SLL_CLK_LCDIF_SEL 68
82#define IMX6SLL_CLK_EPDC_PRE_SEL 69
83#define IMX6SLL_CLK_SPDIF_SEL 70
84#define IMX6SLL_CLK_ECSPI_SEL 71
85#define IMX6SLL_CLK_UART_SEL 72
86#define IMX6SLL_CLK_ARM 73
87#define IMX6SLL_CLK_PERIPH 74
88#define IMX6SLL_CLK_PERIPH2 75
89#define IMX6SLL_CLK_PERIPH2_CLK2 76
90#define IMX6SLL_CLK_PERIPH_CLK2 77
91#define IMX6SLL_CLK_MMDC_PODF 78
92#define IMX6SLL_CLK_AXI_PODF 79
93#define IMX6SLL_CLK_AHB 80
94#define IMX6SLL_CLK_IPG 81
95#define IMX6SLL_CLK_PERCLK 82
96#define IMX6SLL_CLK_USDHC1_PODF 83
97#define IMX6SLL_CLK_USDHC2_PODF 84
98#define IMX6SLL_CLK_USDHC3_PODF 85
99#define IMX6SLL_CLK_SSI1_PRED 86
100#define IMX6SLL_CLK_SSI2_PRED 87
101#define IMX6SLL_CLK_SSI3_PRED 88
102#define IMX6SLL_CLK_SSI1_PODF 89
103#define IMX6SLL_CLK_SSI2_PODF 90
104#define IMX6SLL_CLK_SSI3_PODF 91
105#define IMX6SLL_CLK_PXP_PODF 92
106#define IMX6SLL_CLK_LCDIF_PRED 93
107#define IMX6SLL_CLK_LCDIF_PODF 94
108#define IMX6SLL_CLK_EPDC_SEL 95
109#define IMX6SLL_CLK_EPDC_PODF 96
110#define IMX6SLL_CLK_SPDIF_PRED 97
111#define IMX6SLL_CLK_SPDIF_PODF 98
112#define IMX6SLL_CLK_ECSPI_PODF 99
113#define IMX6SLL_CLK_UART_PODF 100
114
115/* CCGR 0 */
116#define IMX6SLL_CLK_AIPSTZ1 101
117#define IMX6SLL_CLK_AIPSTZ2 102
118#define IMX6SLL_CLK_DCP 103
119#define IMX6SLL_CLK_UART2_IPG 104
120#define IMX6SLL_CLK_UART2_SERIAL 105
121
122/* CCGR 1 */
123#define IMX6SLL_CLK_ECSPI1 106
124#define IMX6SLL_CLK_ECSPI2 107
125#define IMX6SLL_CLK_ECSPI3 108
126#define IMX6SLL_CLK_ECSPI4 109
127#define IMX6SLL_CLK_UART3_IPG 110
128#define IMX6SLL_CLK_UART3_SERIAL 111
129#define IMX6SLL_CLK_UART4_IPG 112
130#define IMX6SLL_CLK_UART4_SERIAL 113
131#define IMX6SLL_CLK_EPIT1 114
132#define IMX6SLL_CLK_EPIT2 115
133#define IMX6SLL_CLK_GPT_BUS 116
134#define IMX6SLL_CLK_GPT_SERIAL 117
135
136/* CCGR2 */
137#define IMX6SLL_CLK_CSI 118
138#define IMX6SLL_CLK_I2C1 119
139#define IMX6SLL_CLK_I2C2 120
140#define IMX6SLL_CLK_I2C3 121
141#define IMX6SLL_CLK_OCOTP 122
142#define IMX6SLL_CLK_LCDIF_APB 123
143#define IMX6SLL_CLK_PXP 124
144
145/* CCGR3 */
146#define IMX6SLL_CLK_UART5_IPG 125
147#define IMX6SLL_CLK_UART5_SERIAL 126
148#define IMX6SLL_CLK_EPDC_AXI 127
149#define IMX6SLL_CLK_EPDC_PIX 128
150#define IMX6SLL_CLK_LCDIF_PIX 129
151#define IMX6SLL_CLK_WDOG1 130
152#define IMX6SLL_CLK_MMDC_P0_FAST 131
153#define IMX6SLL_CLK_MMDC_P0_IPG 132
154#define IMX6SLL_CLK_OCRAM 133
155
156/* CCGR4 */
157#define IMX6SLL_CLK_PWM1 134
158#define IMX6SLL_CLK_PWM2 135
159#define IMX6SLL_CLK_PWM3 136
160#define IMX6SLL_CLK_PWM4 137
161
162/* CCGR 5 */
163#define IMX6SLL_CLK_ROM 138
164#define IMX6SLL_CLK_SDMA 139
165#define IMX6SLL_CLK_KPP 140
166#define IMX6SLL_CLK_WDOG2 141
167#define IMX6SLL_CLK_SPBA 142
168#define IMX6SLL_CLK_SPDIF 143
169#define IMX6SLL_CLK_SPDIF_GCLK 144
170#define IMX6SLL_CLK_SSI1 145
171#define IMX6SLL_CLK_SSI1_IPG 146
172#define IMX6SLL_CLK_SSI2 147
173#define IMX6SLL_CLK_SSI2_IPG 148
174#define IMX6SLL_CLK_SSI3 149
175#define IMX6SLL_CLK_SSI3_IPG 150
176#define IMX6SLL_CLK_UART1_IPG 151
177#define IMX6SLL_CLK_UART1_SERIAL 152
178
179/* CCGR 6 */
180#define IMX6SLL_CLK_USBOH3 153
181#define IMX6SLL_CLK_USDHC1 154
182#define IMX6SLL_CLK_USDHC2 155
183#define IMX6SLL_CLK_USDHC3 156
184
185#define IMX6SLL_CLK_IPP_DI0 157
186#define IMX6SLL_CLK_IPP_DI1 158
187#define IMX6SLL_CLK_LDB_DI0_SEL 159
188#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160
189#define IMX6SLL_CLK_LDB_DI0_DIV_7 161
190#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162
191#define IMX6SLL_CLK_LDB_DI0 163
192#define IMX6SLL_CLK_LDB_DI1_SEL 164
193#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165
194#define IMX6SLL_CLK_LDB_DI1_DIV_7 166
195#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167
196#define IMX6SLL_CLK_LDB_DI1 168
197#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169
198#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170
199#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
200#define IMX6SLL_CLK_EXTERN_AUDIO 172
201
202#define IMX6SLL_CLK_END 173
203
204#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */