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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -04002/*
Hao Zhang8e697a02014-07-09 23:44:46 +03003 * Keystone : Board initialization
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -04004 *
Hao Zhang8e697a02014-07-09 23:44:46 +03005 * (C) Copyright 2014
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -04006 * Texas Instruments Incorporated, <www.ti.com>
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -04007 */
8
9#include <common.h>
Vitaly Andrianov1ee31512016-03-11 08:23:04 -050010#include "board.h"
Simon Glass0af6e2d2019-08-01 09:46:52 -060011#include <env.h>
Hao Zhang95948202014-10-22 16:32:31 +030012#include <spl.h>
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040013#include <exports.h>
14#include <fdt_support.h>
Khoronzhuk, Ivan50df5cc2014-07-09 19:48:40 +030015#include <asm/arch/ddr3.h>
Khoronzhuk, Ivan238de852014-09-29 22:17:24 +030016#include <asm/arch/psc_defs.h>
Lokesh Vutlada18b182015-10-08 11:31:47 +053017#include <asm/arch/clock.h>
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030018#include <asm/ti-common/ti-aemif.h>
Khoronzhuk, Ivanf2c13ba2014-09-29 22:17:22 +030019#include <asm/ti-common/keystone_net.h>
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040020
21DECLARE_GLOBAL_DATA_PTR;
22
Lokesh Vutla56c8f0a2016-04-13 09:50:59 +053023#if defined(CONFIG_TI_AEMIF)
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030024static struct aemif_config aemif_configs[] = {
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040025 { /* CS0 */
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030026 .mode = AEMIF_MODE_NAND,
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040027 .wr_setup = 0xf,
28 .wr_strobe = 0x3f,
29 .wr_hold = 7,
30 .rd_setup = 0xf,
31 .rd_strobe = 0x3f,
32 .rd_hold = 7,
33 .turn_around = 3,
Khoronzhuk, Ivan8062b052014-06-07 05:10:49 +030034 .width = AEMIF_WIDTH_8,
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040035 },
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040036};
Lokesh Vutla56c8f0a2016-04-13 09:50:59 +053037#endif
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040038
39int dram_init(void)
40{
Vitaly Andrianova9554d62015-02-11 14:07:58 -050041 u32 ddr3_size;
42
43 ddr3_size = ddr3_init();
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040044
45 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
46 CONFIG_MAX_RAM_BANK_SIZE);
Lokesh Vutla56c8f0a2016-04-13 09:50:59 +053047#if defined(CONFIG_TI_AEMIF)
Cooper Jr., Franklin6e549452017-06-16 17:25:25 -050048 if (!board_is_k2g_ice())
49 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
Lokesh Vutla56c8f0a2016-04-13 09:50:59 +053050#endif
51
Cooper Jr., Franklin6e549452017-06-16 17:25:25 -050052 if (!board_is_k2g_ice()) {
53 if (ddr3_size)
54 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
55 else
56 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
57 gd->ram_size >> 30);
58 }
Lokesh Vutlab4b5aac2016-08-27 17:19:15 +053059
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040060 return 0;
61}
62
Keerthy3d966e12018-11-27 17:52:41 +053063struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
64{
65 return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
66}
67
Hao Zhang8e697a02014-07-09 23:44:46 +030068int board_init(void)
69{
Nishanth Menon842649d2015-07-22 18:05:43 -050070 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Hao Zhang8e697a02014-07-09 23:44:46 +030071 return 0;
72}
Karicheri, Muralidharan657f6b52014-04-01 15:01:13 -040073
Hao Zhang95948202014-10-22 16:32:31 +030074#ifdef CONFIG_SPL_BUILD
75void spl_board_init(void)
76{
77 spl_init_keystone_plls();
78 preloader_console_init();
79}
80
81u32 spl_boot_device(void)
82{
83#if defined(CONFIG_SPL_SPI_LOAD)
84 return BOOT_DEVICE_SPI;
85#else
86 puts("Unknown boot device\n");
87 hang();
88#endif
89}
90#endif
91
Robert P. J. Day3c757002016-05-19 15:23:12 -040092#ifdef CONFIG_OF_BOARD_SETUP
Simon Glass2aec3cc2014-10-23 18:58:47 -060093int ft_board_setup(void *blob, bd_t *bd)
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040094{
Hao Zhang8e697a02014-07-09 23:44:46 +030095 int lpae;
96 char *env;
97 char *endp;
98 int nbanks;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -040099 u64 size[2];
Hao Zhang8e697a02014-07-09 23:44:46 +0300100 u64 start[2];
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400101 u32 ddr3a_size;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400102
Simon Glass64b723f2017-08-03 12:22:12 -0600103 env = env_get("mem_lpae");
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400104 lpae = env && simple_strtol(env, NULL, 0);
105
106 ddr3a_size = 0;
107 if (lpae) {
Vitaly Andrianov539de5f2016-03-04 10:36:43 -0600108 ddr3a_size = ddr3_get_size();
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400109 if ((ddr3a_size != 8) && (ddr3a_size != 4))
110 ddr3a_size = 0;
111 }
112
113 nbanks = 1;
114 start[0] = bd->bi_dram[0].start;
115 size[0] = bd->bi_dram[0].size;
116
117 /* adjust memory start address for LPAE */
118 if (lpae) {
Hao Zhang8e697a02014-07-09 23:44:46 +0300119 start[0] -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400120 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
121 }
122
123 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
124 size[1] = ((u64)ddr3a_size - 2) << 30;
125 start[1] = 0x880000000;
126 nbanks++;
127 }
128
129 /* reserve memory at start of bank */
Simon Glass64b723f2017-08-03 12:22:12 -0600130 env = env_get("mem_reserve_head");
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400131 if (env) {
132 start[0] += ustrtoul(env, &endp, 0);
133 size[0] -= ustrtoul(env, &endp, 0);
134 }
135
Simon Glass64b723f2017-08-03 12:22:12 -0600136 env = env_get("mem_reserve");
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400137 if (env)
138 size[0] -= ustrtoul(env, &endp, 0);
139
140 fdt_fixup_memory_banks(blob, start, size, nbanks);
141
Nicholas Faustinifdc8c5c2018-10-03 12:58:49 +0200142 return 0;
143}
144
145void ft_board_setup_ex(void *blob, bd_t *bd)
146{
147 int lpae;
148 u64 size;
149 char *env;
150 u64 *reserve_start;
151 int unitrd_fixup = 0;
152
153 env = env_get("mem_lpae");
154 lpae = env && simple_strtol(env, NULL, 0);
155 env = env_get("uinitrd_fixup");
156 unitrd_fixup = env && simple_strtol(env, NULL, 0);
157
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400158 /* Fix up the initrd */
Murali Karicheri1b845322014-07-09 23:44:45 +0300159 if (lpae && unitrd_fixup) {
Nicholas Faustinifdc8c5c2018-10-03 12:58:49 +0200160 int nodeoffset;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400161 int err;
Nicholas Faustinifdc8c5c2018-10-03 12:58:49 +0200162 u64 *prop1, *prop2;
Hao Zhang8e697a02014-07-09 23:44:46 +0300163 u64 initrd_start, initrd_end;
Murali Karicheri1b845322014-07-09 23:44:45 +0300164
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400165 nodeoffset = fdt_path_offset(blob, "/chosen");
166 if (nodeoffset >= 0) {
Nicholas Faustinifdc8c5c2018-10-03 12:58:49 +0200167 prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400168 "linux,initrd-start", NULL);
Nicholas Faustinifdc8c5c2018-10-03 12:58:49 +0200169 prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400170 "linux,initrd-end", NULL);
171 if (prop1 && prop2) {
Nicholas Faustinifdc8c5c2018-10-03 12:58:49 +0200172 initrd_start = __be64_to_cpu(*prop1);
Hao Zhang8e697a02014-07-09 23:44:46 +0300173 initrd_start -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400174 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
175 initrd_start = __cpu_to_be64(initrd_start);
Nicholas Faustinifdc8c5c2018-10-03 12:58:49 +0200176 initrd_end = __be64_to_cpu(*prop2);
Hao Zhang8e697a02014-07-09 23:44:46 +0300177 initrd_end -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400178 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
179 initrd_end = __cpu_to_be64(initrd_end);
180
181 err = fdt_delprop(blob, nodeoffset,
182 "linux,initrd-start");
183 if (err < 0)
184 puts("error deleting initrd-start\n");
185
186 err = fdt_delprop(blob, nodeoffset,
187 "linux,initrd-end");
188 if (err < 0)
189 puts("error deleting initrd-end\n");
190
191 err = fdt_setprop(blob, nodeoffset,
192 "linux,initrd-start",
193 &initrd_start,
194 sizeof(initrd_start));
195 if (err < 0)
196 puts("error adding initrd-start\n");
197
198 err = fdt_setprop(blob, nodeoffset,
199 "linux,initrd-end",
200 &initrd_end,
201 sizeof(initrd_end));
202 if (err < 0)
203 puts("error adding linux,initrd-end\n");
204 }
205 }
206 }
Simon Glass2aec3cc2014-10-23 18:58:47 -0600207
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400208 if (lpae) {
209 /*
210 * the initrd and other reserved memory areas are
211 * embedded in in the DTB itslef. fix up these addresses
212 * to 36 bit format
213 */
214 reserve_start = (u64 *)((char *)blob +
215 fdt_off_mem_rsvmap(blob));
216 while (1) {
217 *reserve_start = __cpu_to_be64(*reserve_start);
218 size = __cpu_to_be64(*(reserve_start + 1));
219 if (size) {
Hao Zhang8e697a02014-07-09 23:44:46 +0300220 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400221 *reserve_start +=
222 CONFIG_SYS_LPAE_SDRAM_BASE;
223 *reserve_start =
224 __cpu_to_be64(*reserve_start);
225 } else {
226 break;
227 }
228 reserve_start += 2;
229 }
230 }
Vitaly Andrianov19173012014-10-22 17:47:58 +0300231
232 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
Vitaly Andrianov7bcf4d62014-04-04 13:16:53 -0400233}
Robert P. J. Day3c757002016-05-19 15:23:12 -0400234#endif /* CONFIG_OF_BOARD_SETUP */
Cooper Jr., Franklin74f22ca2017-06-16 17:25:15 -0500235
236#if defined(CONFIG_DTB_RESELECT)
237int __weak embedded_dtb_select(void)
238{
239 return 0;
240}
241#endif