Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2006 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /************************************************************************ |
| 25 | * pcs440ep.h - configuration for PCS440EP board |
| 26 | ***********************************************************************/ |
| 27 | #ifndef __CONFIG_H |
| 28 | #define __CONFIG_H |
| 29 | |
Bartlomiej Sieka | 183fe0a | 2008-03-20 23:23:13 +0100 | [diff] [blame] | 30 | |
| 31 | /* new uImage format support */ |
| 32 | #define CONFIG_FIT 1 |
| 33 | #define CONFIG_OF_LIBFDT 1 |
| 34 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ |
| 35 | |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 36 | /*----------------------------------------------------------------------- |
| 37 | * High Level Configuration Options |
| 38 | *----------------------------------------------------------------------*/ |
| 39 | #define CONFIG_PCS440EP 1 /* Board is PCS440EP */ |
| 40 | #define CONFIG_440EP 1 /* Specific PPC440EP support */ |
Grzegorz Bernacki | 837bc5b | 2007-06-15 11:19:28 +0200 | [diff] [blame] | 41 | #define CONFIG_440 1 /* ... PPC440 family */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 42 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 43 | |
| 44 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 |
| 45 | |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 46 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
| 47 | |
| 48 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| 49 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
| 50 | |
| 51 | /*----------------------------------------------------------------------- |
| 52 | * Base addresses -- Note these are effective addresses where the |
| 53 | * actual resources get mapped (not physical addresses) |
| 54 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 55 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ |
| 56 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ |
| 57 | #define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN) |
| 58 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
| 59 | #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */ |
| 60 | #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ |
| 61 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 |
| 62 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 |
| 63 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 64 | |
| 65 | /*Don't change either of these*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 66 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 67 | /*Don't change either of these*/ |
| 68 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 69 | #define CONFIG_SYS_USB_DEVICE 0x50000000 |
| 70 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 71 | |
| 72 | /*----------------------------------------------------------------------- |
| 73 | * Initial RAM & stack pointer (placed in SDRAM) |
| 74 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 75 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
| 76 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 77 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 78 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 79 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 80 | |
| 81 | /*----------------------------------------------------------------------- |
| 82 | * Serial Port |
| 83 | *----------------------------------------------------------------------*/ |
Stefan Roese | 3ddce57 | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 84 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
| 85 | #define CONFIG_SYS_NS16550 |
| 86 | #define CONFIG_SYS_NS16550_SERIAL |
| 87 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 88 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clk used */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 90 | #define CONFIG_BAUDRATE 115200 |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 91 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 93 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| 94 | |
| 95 | /*----------------------------------------------------------------------- |
| 96 | * Environment |
| 97 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 98 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 99 | |
| 100 | /*----------------------------------------------------------------------- |
| 101 | * FLASH related |
| 102 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 103 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| 104 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 105 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 106 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 107 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 108 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ |
| 110 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
| 111 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 112 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 113 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 114 | |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 115 | #ifdef CONFIG_ENV_IS_IN_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 116 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 117 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 118 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 119 | |
| 120 | #define CONFIG_ENV_OVERWRITE 1 |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 121 | |
| 122 | /* Address and size of Redundant Environment Sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 123 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| 124 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 125 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 126 | |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 127 | #define ENV_NAME_REVLEV "revision_level" |
| 128 | #define ENV_NAME_SOLDER "solder_switch" |
| 129 | #define ENV_NAME_DIP "dip" |
| 130 | |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 131 | /*----------------------------------------------------------------------- |
| 132 | * DDR SDRAM |
| 133 | *----------------------------------------------------------------------*/ |
| 134 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ |
| 135 | #undef CONFIG_DDR_ECC /* don't use ECC */ |
Stefan Roese | 82041f5 | 2006-06-13 18:55:07 +0200 | [diff] [blame] | 136 | #define SPD_EEPROM_ADDRESS {0x50} |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 137 | #define CONFIG_PROG_SDRAM_TLB 1 |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 138 | |
| 139 | /*----------------------------------------------------------------------- |
| 140 | * I2C |
| 141 | *----------------------------------------------------------------------*/ |
| 142 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
| 143 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
Stefan Roese | 3b01e6b | 2010-04-01 14:37:24 +0200 | [diff] [blame] | 144 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 145 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
| 146 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 147 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 148 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa4>>1) |
| 149 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 150 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 151 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 152 | |
| 153 | #define CONFIG_PREBOOT "echo;" \ |
Wolfgang Denk | 1baed66 | 2008-03-03 12:16:44 +0100 | [diff] [blame] | 154 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 155 | "echo" |
| 156 | |
| 157 | #undef CONFIG_BOOTARGS |
| 158 | |
| 159 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 160 | "netdev=eth0\0" \ |
| 161 | "hostname=pcs440ep\0" \ |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 162 | "use_eeprom_ethaddr=default\0" \ |
| 163 | "cs_test=off\0" \ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 164 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 165 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 166 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 167 | "addip=setenv bootargs ${bootargs} " \ |
| 168 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 169 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 170 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ |
| 171 | "flash_nfs=run nfsargs addip addtty;" \ |
| 172 | "bootm ${kernel_addr}\0" \ |
| 173 | "flash_self=run ramargs addip addtty;" \ |
| 174 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 175 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ |
| 176 | "bootm\0" \ |
| 177 | "rootpath=/opt/eldk/ppc_4xx\0" \ |
| 178 | "bootfile=/tftpboot/pcs440ep/uImage\0" \ |
Wolfgang Denk | f08517b | 2006-06-07 11:36:02 +0200 | [diff] [blame] | 179 | "kernel_addr=FFF00000\0" \ |
| 180 | "ramdisk_addr=FFF00000\0" \ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 181 | "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \ |
Wolfgang Denk | f08517b | 2006-06-07 11:36:02 +0200 | [diff] [blame] | 182 | "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ |
| 183 | "cp.b 100000 FFFA0000 60000\0" \ |
Detlev Zundel | 406e578 | 2008-03-06 16:45:53 +0100 | [diff] [blame] | 184 | "upd=run load update\0" \ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 185 | "" |
| 186 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 187 | |
| 188 | #if 0 |
| 189 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
| 190 | #else |
| 191 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 192 | #endif |
| 193 | |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 194 | /* check U-Boot image with SHA1 sum */ |
| 195 | #define CONFIG_SHA1_CHECK_UB_IMG 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 196 | #define CONFIG_SHA1_START CONFIG_SYS_MONITOR_BASE |
| 197 | #define CONFIG_SHA1_LEN CONFIG_SYS_MONITOR_LEN |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 198 | |
| 199 | /*----------------------------------------------------------------------- |
| 200 | * Definitions for status LED |
| 201 | */ |
| 202 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
| 203 | #define CONFIG_BOARD_SPECIFIC_LED 1 |
| 204 | |
Heiko Schocher | 30b4c25 | 2007-07-11 18:39:11 +0200 | [diff] [blame] | 205 | #define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 206 | #define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 207 | #define STATUS_LED_STATE STATUS_LED_OFF |
Heiko Schocher | 30b4c25 | 2007-07-11 18:39:11 +0200 | [diff] [blame] | 208 | #define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 209 | #define STATUS_LED_PERIOD1 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 210 | #define STATUS_LED_STATE1 STATUS_LED_ON |
Heiko Schocher | 30b4c25 | 2007-07-11 18:39:11 +0200 | [diff] [blame] | 211 | #define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 212 | #define STATUS_LED_PERIOD2 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 213 | #define STATUS_LED_STATE2 STATUS_LED_OFF |
Heiko Schocher | 30b4c25 | 2007-07-11 18:39:11 +0200 | [diff] [blame] | 214 | #define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 215 | #define STATUS_LED_PERIOD3 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 216 | #define STATUS_LED_STATE3 STATUS_LED_OFF |
| 217 | |
| 218 | #define CONFIG_SHOW_BOOT_PROGRESS 1 |
| 219 | |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 220 | #define CONFIG_BAUDRATE 115200 |
| 221 | |
| 222 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 224 | |
Ben Warren | 3a918a6 | 2008-10-27 23:50:15 -0700 | [diff] [blame] | 225 | #define CONFIG_PPC4xx_EMAC |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 226 | #define CONFIG_MII 1 /* MII PHY management */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 227 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
| 228 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
| 229 | #define CONFIG_PHY1_ADDR 2 |
| 230 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 231 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 232 | |
| 233 | #define CONFIG_NETCONSOLE /* include NetConsole support */ |
| 234 | |
| 235 | /* Partitions */ |
| 236 | #define CONFIG_MAC_PARTITION |
| 237 | #define CONFIG_DOS_PARTITION |
| 238 | #define CONFIG_ISO_PARTITION |
| 239 | |
| 240 | #ifdef CONFIG_440EP |
| 241 | /* USB */ |
| 242 | #define CONFIG_USB_OHCI |
| 243 | #define CONFIG_USB_STORAGE |
| 244 | |
| 245 | /*Comment this out to enable USB 1.1 device*/ |
| 246 | #define USB_2_0_DEVICE |
| 247 | #endif /*CONFIG_440EP*/ |
| 248 | |
| 249 | #ifdef DEBUG |
| 250 | #define CONFIG_PANIC_HANG |
| 251 | #else |
| 252 | #define CONFIG_HW_WATCHDOG /* watchdog */ |
| 253 | #endif |
| 254 | |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 255 | |
Jon Loeliger | aa2d2c2 | 2007-07-04 22:33:17 -0500 | [diff] [blame] | 256 | /* |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 257 | * BOOTP options |
| 258 | */ |
| 259 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 260 | #define CONFIG_BOOTP_BOOTPATH |
| 261 | #define CONFIG_BOOTP_GATEWAY |
| 262 | #define CONFIG_BOOTP_HOSTNAME |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 263 | |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 264 | |
| 265 | /* |
Jon Loeliger | aa2d2c2 | 2007-07-04 22:33:17 -0500 | [diff] [blame] | 266 | * Command line configuration. |
| 267 | */ |
| 268 | #include <config_cmd_default.h> |
| 269 | #define CONFIG_CMD_ASKENV |
| 270 | #define CONFIG_CMD_DHCP |
| 271 | #define CONFIG_CMD_DIAG |
| 272 | #define CONFIG_CMD_EEPROM |
| 273 | #define CONFIG_CMD_ELF |
Heiko Schocher | 2559e0f | 2007-08-28 17:39:14 +0200 | [diff] [blame] | 274 | #define CONFIG_CMD_EXT2 |
| 275 | #define CONFIG_CMD_FAT |
Jon Loeliger | aa2d2c2 | 2007-07-04 22:33:17 -0500 | [diff] [blame] | 276 | #define CONFIG_CMD_I2C |
Heiko Schocher | 2559e0f | 2007-08-28 17:39:14 +0200 | [diff] [blame] | 277 | #define CONFIG_CMD_IDE |
Jon Loeliger | aa2d2c2 | 2007-07-04 22:33:17 -0500 | [diff] [blame] | 278 | #define CONFIG_CMD_IRQ |
| 279 | #define CONFIG_CMD_MII |
| 280 | #define CONFIG_CMD_NET |
| 281 | #define CONFIG_CMD_NFS |
| 282 | #define CONFIG_CMD_PCI |
| 283 | #define CONFIG_CMD_PING |
| 284 | #define CONFIG_CMD_REGINFO |
Heiko Schocher | 2559e0f | 2007-08-28 17:39:14 +0200 | [diff] [blame] | 285 | #define CONFIG_CMD_REISER |
Jon Loeliger | aa2d2c2 | 2007-07-04 22:33:17 -0500 | [diff] [blame] | 286 | #define CONFIG_CMD_SDRAM |
Jon Loeliger | aa2d2c2 | 2007-07-04 22:33:17 -0500 | [diff] [blame] | 287 | #define CONFIG_CMD_USB |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 288 | |
Jon Loeliger | aa2d2c2 | 2007-07-04 22:33:17 -0500 | [diff] [blame] | 289 | #define CONFIG_SUPPORT_VFAT |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 290 | |
| 291 | /* |
| 292 | * Miscellaneous configurable options |
| 293 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 294 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 295 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
Jon Loeliger | aa2d2c2 | 2007-07-04 22:33:17 -0500 | [diff] [blame] | 296 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 297 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 298 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 299 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 300 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 301 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 302 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 303 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 304 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 305 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 306 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 307 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 308 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 309 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 310 | #define CONFIG_LYNXKDI 1 /* support kdi files */ |
| 311 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 312 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 313 | |
| 314 | /*----------------------------------------------------------------------- |
| 315 | * PCI stuff |
| 316 | *----------------------------------------------------------------------- |
| 317 | */ |
| 318 | /* General PCI */ |
| 319 | #define CONFIG_PCI /* include pci support */ |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 320 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 321 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
| 322 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 323 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 324 | |
| 325 | /* Board-specific PCI */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 326 | #define CONFIG_SYS_PCI_TARGET_INIT |
| 327 | #define CONFIG_SYS_PCI_MASTER_INIT |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 328 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 329 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
| 330 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 331 | |
| 332 | /* |
| 333 | * For booting Linux, the board info and command line data |
| 334 | * have to be in the first 8 MB of memory, since this is |
| 335 | * the maximum mapped by the Linux kernel during initialization. |
| 336 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 337 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 338 | |
| 339 | /*----------------------------------------------------------------------- |
| 340 | * External Bus Controller (EBC) Setup |
| 341 | *----------------------------------------------------------------------*/ |
| 342 | #define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */ |
| 343 | #define FLASH_BASE1_PRELIM 0xFFF80000 /* FLASH bank #1 */ |
| 344 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 345 | #define CONFIG_SYS_FLASH FLASH_BASE0_PRELIM |
| 346 | #define CONFIG_SYS_SRAM 0xF1000000 |
| 347 | #define CONFIG_SYS_FPGA 0xF2000000 |
| 348 | #define CONFIG_SYS_CF1 0xF0000000 |
| 349 | #define CONFIG_SYS_CF2 0xF0100000 |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 350 | |
| 351 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 352 | #define CONFIG_SYS_EBC_PB0AP 0x02010000 /* TWT=4,OEN=1 */ |
| 353 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 354 | |
| 355 | /* Memory Bank 1 (SRAM) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 356 | #define CONFIG_SYS_EBC_PB1AP 0x01810040 /* TWT=3,OEN=1,BEM=1 */ |
| 357 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 358 | |
| 359 | /* Memory Bank 2 (FPGA) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 360 | #define CONFIG_SYS_EBC_PB2AP 0x01010440 /* TWT=2,OEN=1,TH=2,BEM=1 */ |
| 361 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 362 | |
| 363 | /* Memory Bank 3 (CompactFlash) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 364 | #define CONFIG_SYS_EBC_PB3AP 0x080BD400 |
| 365 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 366 | |
| 367 | /* Memory Bank 4 (CompactFlash) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 368 | #define CONFIG_SYS_EBC_PB4AP 0x080BD400 |
| 369 | #define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 370 | |
| 371 | /*----------------------------------------------------------------------- |
| 372 | * PPC440 GPIO Configuration |
| 373 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 374 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 375 | { \ |
| 376 | /* GPIO Core 0 */ \ |
Stefan Roese | 843b3a8 | 2007-06-15 07:39:43 +0200 | [diff] [blame] | 377 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ |
| 378 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ |
| 379 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ |
| 380 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ |
| 381 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ |
| 382 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ |
| 383 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \ |
| 384 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \ |
| 385 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \ |
| 386 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \ |
| 387 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \ |
| 388 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \ |
| 389 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \ |
| 390 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \ |
| 391 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \ |
| 392 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \ |
| 393 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \ |
| 394 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \ |
| 395 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \ |
| 396 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \ |
| 397 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \ |
| 398 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \ |
| 399 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \ |
| 400 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \ |
| 401 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \ |
| 402 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \ |
| 403 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \ |
| 404 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ |
| 405 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \ |
| 406 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ |
| 407 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ |
| 408 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 409 | }, \ |
| 410 | { \ |
| 411 | /* GPIO Core 1 */ \ |
Stefan Roese | 843b3a8 | 2007-06-15 07:39:43 +0200 | [diff] [blame] | 412 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \ |
| 413 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \ |
| 414 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ |
| 415 | {GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ |
| 416 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \ |
| 417 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \ |
| 418 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ |
| 419 | {GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \ |
| 420 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \ |
| 421 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \ |
| 422 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \ |
| 423 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \ |
| 424 | {GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ |
| 425 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ |
| 426 | {GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ |
| 427 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ |
| 428 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ |
| 429 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \ |
| 430 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \ |
| 431 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \ |
| 432 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \ |
| 433 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \ |
| 434 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \ |
| 435 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \ |
| 436 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \ |
| 437 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \ |
| 438 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \ |
| 439 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \ |
| 440 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \ |
| 441 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \ |
| 442 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \ |
| 443 | {GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \ |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 444 | } \ |
| 445 | } |
| 446 | |
Jon Loeliger | aa2d2c2 | 2007-07-04 22:33:17 -0500 | [diff] [blame] | 447 | #if defined(CONFIG_CMD_KGDB) |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 448 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 449 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 450 | #endif |
| 451 | |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 452 | /*----------------------------------------------------------------------- |
| 453 | * IDE/ATA stuff Supports IDE harddisk |
| 454 | *----------------------------------------------------------------------- |
| 455 | */ |
| 456 | |
| 457 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
| 458 | |
| 459 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
| 460 | #undef CONFIG_IDE_LED /* LED for ide not supported */ |
| 461 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 462 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
| 463 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 464 | |
| 465 | #define CONFIG_IDE_PREINIT 1 |
| 466 | #define CONFIG_IDE_RESET 1 |
| 467 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 468 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 469 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 470 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF1 |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 471 | |
| 472 | /* Offset for data I/O */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 473 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 474 | |
| 475 | /* Offset for normal register accesses */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 476 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 477 | |
| 478 | /* Offset for alternate registers */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 479 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x0000) |
Heiko Schocher | 633e03a | 2007-06-22 19:11:54 +0200 | [diff] [blame] | 480 | |
Stefan Roese | 9eba0c8 | 2006-06-02 16:18:04 +0200 | [diff] [blame] | 481 | #endif /* __CONFIG_H */ |