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git01.mediatek.com / filogic / uboot / e612f6803a6d9386f9b73b677ede15b658c0faab / . / arch / sh / include / asm / cpu_sh7750.h
blob: e0cafbdbba0cad66a571ea344106fb70cbc3e7af [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]2/*
3 * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
4 *
Wolfgang Denk0a5c2142007-12-27 01:52:50 +0100[diff] [blame]5 * SH7750/SH7750S/SH7750R/SH7751/SH7751R
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]6 * Internal I/O register
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]7 */
8
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]9#ifndef _ASM_CPU_SH7750_H_
10#define _ASM_CPU_SH7750_H_
11
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]12#ifdef CONFIG_CPU_TYPE_R
13#define CACHE_OC_NUM_WAYS 2
Nobuhiro Iwamatsu53b31432008-03-12 12:10:28 +0900[diff] [blame]14#define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]15#else
16#define CACHE_OC_NUM_WAYS 1
Nobuhiro Iwamatsu53b31432008-03-12 12:10:28 +0900[diff] [blame]17#define CCR_CACHE_INIT 0x0000090B
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]18#endif
19
20/* OCN */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]21#define PTEH 0xFF000000
22#define PTEL 0xFF000004
23#define TTB 0xFF000008
24#define TEA 0xFF00000C
25#define MMUCR 0xFF000010
26#define BASRA 0xFF000014
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]27#define BASRB 0xFF000018
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]28#define CCR 0xFF00001C
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]29#define TRA 0xFF000020
30#define EXPEVT 0xFF000024
31#define INTEVT 0xFF000028
32#define PTEA 0xFF000034
33#define QACR0 0xFF000038
34#define QACR1 0xFF00003C
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]35
36/* UBC */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]37#define BARA 0xFF200000
38#define BAMRA 0xFF200004
39#define BBRA 0xFF200008
40#define BARB 0xFF20000C
41#define BAMRB 0xFF200010
42#define BBRB 0xFF200014
43#define BDRB 0xFF200018
44#define BDMRB 0xFF20001C
45#define BRCR 0xFF200020
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]46
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]47/* BSC */
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]48#define BCR1 0xFF800000
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]49#define BCR2 0xFF800004
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]50#define BCR3 0xFF800050
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]51#define BCR4 0xFE0A00F0
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]52#define WCR1 0xFF800008
53#define WCR2 0xFF80000C
54#define WCR3 0xFF800010
55#define MCR 0xFF800014
56#define PCR 0xFF800018
57#define RTCSR 0xFF80001C
58#define RTCNT 0xFF800020
59#define RTCOR 0xFF800024
60#define RFCR 0xFF800028
61#define PCTRA 0xFF80002C
62#define PDTRA 0xFF800030
63#define PCTRB 0xFF800040
64#define PDTRB 0xFF800044
65#define GPIOIC 0xFF800048
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]66
67/* DMAC */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]68#define SAR0 0xFFA00000
69#define DAR0 0xFFA00004
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]70#define DMATCR0 0xFFA00008
71#define CHCR0 0xFFA0000C
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]72#define SAR1 0xFFA00010
73#define DAR1 0xFFA00014
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]74#define DMATCR1 0xFFA00018
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]75#define CHCR1 0xFFA0001C
76#define SAR2 0xFFA00020
77#define DAR2 0xFFA00024
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]78#define DMATCR2 0xFFA00028
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]79#define CHCR2 0xFFA0002C
80#define SAR3 0xFFA00030
81#define DAR3 0xFFA00034
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]82#define DMATCR3 0xFFA00038
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]83#define CHCR3 0xFFA0003C
84#define DMAOR 0xFFA00040
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]85#define SAR4 0xFFA00050
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]86#define DAR4 0xFFA00054
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]87#define DMATCR4 0xFFA00058
88
89/* CPG */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]90#define FRQCR 0xFFC00000
91#define STBCR 0xFFC00004
92#define WTCNT 0xFFC00008
93#define WTCSR 0xFFC0000C
94#define STBCR2 0xFFC00010
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]95
96/* RTC */
97#define R64CNT 0xFFC80000
98#define RSECCNT 0xFFC80004
99#define RMINCNT 0xFFC80008
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]100#define RHRCNT 0xFFC8000C
101#define RWKCNT 0xFFC80010
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]102#define RDAYCNT 0xFFC80014
103#define RMONCNT 0xFFC80018
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]104#define RYRCNT 0xFFC8001C
105#define RSECAR 0xFFC80020
106#define RMINAR 0xFFC80024
107#define RHRAR 0xFFC80028
108#define RWKAR 0xFFC8002C
109#define RDAYAR 0xFFC80030
110#define RMONAR 0xFFC80034
111#define RCR1 0xFFC80038
112#define RCR2 0xFFC8003C
113#define RCR3 0xFFC80050
114#define RYRAR 0xFFC80054
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]115
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]116/* ICR */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]117#define ICR 0xFFD00000
118#define IPRA 0xFFD00004
119#define IPRB 0xFFD00008
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]120#define IPRC 0xFFD0000C
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]121#define IPRD 0xFFD00010
122#define INTPRI 0xFE080000
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]123#define INTREQ 0xFE080020
124#define INTMSK 0xFE080040
125#define INTMSKCL 0xFE080060
126
127/* CPG */
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]128#define CLKSTP 0xFE0A0000
129#define CLKSTPCLR 0xFE0A0008
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]130
131/* TMU */
Nobuhiro Iwamatsue763f1a2012-08-21 13:14:46 +0900[diff] [blame]132#define TMU_BASE 0xFFD80000
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]133
134/* SCI */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]135#define SCSMR1 0xFFE00000
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]136#define SCF0_BASE SCSMR1
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]137
138/* SCIF */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]139#define SCSMR2 0xFFE80000
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]140#define SCIF1_BASE SCSMR2
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]141
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]142/* H-UDI */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]143#define SDIR 0xFFF00000
144#define SDDR 0xFFF00008
145#define SDINT 0xFFF00014
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]146
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]147#endif /* _ASM_CPU_SH7750_H_ */