| Jim Liu | 147c000 | 2022-09-27 16:45:15 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | |
| 3 | #ifndef _NPCM_RST_H_ |
| 4 | #define _NPCM_RST_H_ |
| 5 | |
| 6 | /* Watchdog Timer Controller Register */ |
| 7 | #define WTCR0_REG 0xF000801C |
| 8 | #define WTCR_WTR BIT(0) |
| 9 | #define WTCR_WTRE BIT(1) |
| 10 | #define WTCR_WTE BIT(7) |
| 11 | |
| 12 | /* Reset status bits */ |
| 13 | #define PORST BIT(31) |
| 14 | #define CORST BIT(30) |
| 15 | #define WD0RST BIT(29) |
| 16 | #define SW1RST BIT(28) |
| 17 | #define SW2RST BIT(27) |
| 18 | #define SW3RST BIT(26) |
| 19 | #define SW4RST BIT(25) |
| 20 | #define WD1RST BIT(24) |
| 21 | #define WD2RST BIT(23) |
| 22 | #define RST_STS_MASK GENMASK(31, 23) |
| 23 | |
| 24 | int npcm_get_reset_status(void); |
| 25 | |
| 26 | #endif |