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git01.mediatek.com / filogic / uboot / e5f2b2268b7b431b7a7deb50eaaae645892827c3 / . / arch / arm / dts / imx7ulp.dtsi
blob: a8458f89d5fca41f4aaacdee6d2dcdf0c8d788eb [file] [log] [blame]
Peng Fanadaf8be2017-02-22 16:21:54 +0800[diff] [blame]1/*
2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx7ulp-clock.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/gpio/gpio.h>
12#include "skeleton.dtsi"
13#include "imx7ulp-pinfunc.h"
14
15/ {
16 interrupt-parent = <&intc>;
17
18 aliases {
19 gpio0 = &gpio0;
20 gpio1 = &gpio1;
21 gpio2 = &gpio2;
22 gpio3 = &gpio3;
23 mmc0 = &usdhc0;
24 mmc1 = &usdhc1;
25 serial0 = &lpuart4;
26 serial1 = &lpuart5;
27 serial2 = &lpuart6;
28 serial3 = &lpuart7;
29 usbphy0 = &usbphy1;
Peng Fan18a912d2018-01-02 15:41:53 +0800[diff] [blame]30 i2c4 = &lpi2c4;
31 i2c5 = &lpi2c5;
32 i2c6 = &lpi2c6;
33 i2c7 = &lpi2c7;
Peng Fanadaf8be2017-02-22 16:21:54 +0800[diff] [blame]34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 compatible = "arm,cortex-a7";
42 device_type = "cpu";
43 reg = <0>;
44 };
45 };
46
47 reserved-memory {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges;
51
52 /* global autoconfigured region for contiguous allocations */
53 linux,cma {
54 compatible = "shared-dma-pool";
55 reusable;
56 size = <0xC000000>;
57 alignment = <0x2000>;
58 linux,cma-default;
59 };
60
61 rpmsg_reserved: rpmsg@9FFF0000 {
62 no-map;
63 reg = <0x9FF00000 0x100000>;
64 };
65
66 };
67
68 intc: interrupt-controller@40021000 {
69 compatible = "arm,cortex-a7-gic";
70 #interrupt-cells = <3>;
71 interrupt-controller;
72 reg = <0x40021000 0x1000>,
73 <0x40022000 0x100>;
74 };
75
76 clocks {
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 ckil: clock@0 {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <32768>;
84 clock-output-names = "ckil";
85 };
86
87 osc: clock@1 {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <24000000>;
91 clock-output-names = "osc";
92 };
93
94 sirc: clock@2 {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <16000000>;
98 clock-output-names = "sirc";
99 };
100
101 firc: clock@3 {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <48000000>;
105 clock-output-names = "firc";
106 };
107
108 upll: clock@4 {
109 compatible = "fixed-clock";
110 #clock-cells = <0>;
111 clock-frequency = <480000000>;
112 clock-output-names = "upll";
113 };
114
115 mpll: clock@5 {
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 clock-frequency = <480000000>;
119 clock-output-names = "mpll";
120 };
121 };
122
123 sram: sram@20000000 {
124 compatible = "fsl,lpm-sram";
125 reg = <0x1fffc000 0x4000>;
126 };
127
128 ahbbridge0: ahb-bridge0@40000000 {
129 compatible = "fsl,aips-bus", "simple-bus";
130 #address-cells = <1>;
131 #size-cells = <1>;
132 reg = <0x40000000 0x800000>;
133 ranges;
134
135 edma0: dma-controller@40080000 {
136 #dma-cells = <2>;
137 compatible = "nxp,imx7ulp-edma";
138 reg = <0x40080000 0x2000>,
139 <0x40210000 0x1000>;
140 dma-channels = <32>;
141 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
158 clock-names = "dma", "dmamux0";
159 clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>;
160 };
161
162 mu: mu@40220000 {
163 compatible = "fsl,imx7ulp-mu", "fsl,imx6sx-mu";
164 reg = <0x40220000 0x1000>;
165 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
167 status = "okay";
168 };
169
170 nmi: nmi@40220000 {
171 compatible = "fsl,imx7ulp-nmi";
172 reg = <0x40220000 0x1000>;
173 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
174 status = "okay";
175 };
176
177 rpmsg: rpmsg{
178 compatible = "fsl,imx7ulp-rpmsg";
179 memory-region = <&rpmsg_reserved>;
180 status = "disabled";
181 };
182
183 snvs: snvs@40230000 {
184 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
185 reg = <0x40230000 0x10000>;
186
187 snvs_rtc: snvs-rtc-lp{
188 compatible = "fsl,sec-v4.0-mon-rtc-lp";
189 regmap =<&snvs>;
190 offset = <0x34>;
191 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
192 clock-names = "snvs-rtc";
193 clocks = <&clks IMX7ULP_CLK_SNVS>;
194 };
195 };
196
197 tpm5: tpm@40260000 {
198 compatible = "fsl,imx7ulp-tpm";
199 reg = <0x40260000 0x1000>;
200 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&clks IMX7ULP_CLK_LPTPM5>;
202 };
203
204 lpit: 1@40270000 {
205 compatible = "fsl,imx-lpit";
206 reg = <0x40270000 0x1000>;
207 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
208 /* clocks = <&lpclk>;*/
209 clocks = <&clks IMX7ULP_CLK_LPIT1>;
210 assigned-clock-rates = <48000000>;
211 assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
212 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
213 };
214
215 lpi2c4: lpi2c4@402B0000 {
216 compatible = "fsl,imx7ulp-lpi2c";
217 reg = <0x402B0000 0x10000>;
218 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clks IMX7ULP_CLK_LPI2C4>;
220 clock-names = "ipg";
221 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
222 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
223 assigned-clock-rates = <48000000>;
224 status = "disabled";
225 };
226
227 lpi2c5: lpi2c4@402C0000 {
228 compatible = "fsl,imx7ulp-lpi2c";
229 reg = <0x402C0000 0x10000>;
230 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&clks IMX7ULP_CLK_LPI2C5>;
232 clock-names = "ipg";
233 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
234 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
235 assigned-clock-rates = <48000000>;
236 status = "disabled";
237 };
238
239 lpspi2: lpspi@40290000 {
240 compatible = "fsl,imx7ulp-spi";
241 reg = <0x40290000 0x10000>;
242 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&clks IMX7ULP_CLK_LPSPI2>;
244 clock-names = "ipg";
245 assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
246 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
247 assigned-clock-rates = <48000000>;
248 status = "disabled";
249 };
250
251 lpspi3: lpspi@402A0000 {
252 compatible = "fsl,imx7ulp-spi";
253 reg = <0x402A0000 0x10000>;
254 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&clks IMX7ULP_CLK_LPSPI3>;
256 clock-names = "ipg";
257 assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
258 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
259 assigned-clock-rates = <48000000>;
260 status = "disabled";
261 };
262
263 lpuart4: serial@402D0000 {
264 compatible = "fsl,imx7ulp-lpuart";
265 reg = <0x402D0000 0x1000>;
266 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clks IMX7ULP_CLK_LPUART4>;
268 clock-names = "ipg";
269 assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
270 assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
271 assigned-clock-rates = <24000000>;
272 status = "disabled";
273 };
274
275 lpuart5: serial@402E0000 {
276 compatible = "fsl,imx7ulp-lpuart";
277 reg = <0x402E0000 0x1000>;
278 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clks IMX7ULP_CLK_LPUART5>;
280 clock-names = "ipg";
281 assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
282 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
283 assigned-clock-rates = <48000000>;
284 dmas = <&edma0 0 20>, <&edma0 0 19>;
285 dma-names = "tx","rx";
286 status = "disabled";
287 };
288
289 usbotg1: usb@40330000 {
290 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb",
291 "fsl,imx27-usb";
292 reg = <0x40330000 0x200>;
293 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&clks IMX7ULP_CLK_USB0>;
295 fsl,usbphy = <&usbphy1>;
296 fsl,usbmisc = <&usbmisc1 0>;
297 ahb-burst-config = <0x0>;
298 tx-burst-size-dword = <0x8>;
299 rx-burst-size-dword = <0x8>;
300 status = "disabled";
301 };
302
303 usbmisc1: usbmisc@40330200 {
304 #index-cells = <1>;
305 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc",
306 "fsl,imx6q-usbmisc";
307 reg = <0x40330200 0x200>;
308 };
309
310 usbphy1: usbphy@0x40350000 {
311 compatible = "fsl,imx7ulp-usbphy",
312 "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
313 reg = <0x40350000 0x1000>;
314 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clks IMX7ULP_CLK_USB_PHY>;
316 nxp,sim = <&sim>;
317 };
318
319 usdhc0: usdhc@40370000 {
320 compatible = "fsl,imx7ulp-usdhc";
321 reg = <0x40370000 0x10000>;
322 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
324 <&clks IMX7ULP_CLK_NIC1_DIV>,
325 <&clks IMX7ULP_CLK_USDHC0>;
326 clock-names ="ipg", "ahb", "per";
327 bus-width = <4>;
328 fsl,tuning-start-tap = <20>;
329 fsl,tuning-step= <2>;
330 status = "disabled";
331 };
332
333 usdhc1: usdhc@40380000 {
334 compatible = "fsl,imx7ulp-usdhc";
335 reg = <0x40380000 0x10000>;
336 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
338 <&clks IMX7ULP_CLK_NIC1_DIV>,
339 <&clks IMX7ULP_CLK_USDHC1>;
340 clock-names ="ipg", "ahb", "per";
341 bus-width = <4>;
342 fsl,tuning-start-tap = <20>;
343 fsl,tuning-step= <2>;
344 status = "disabled";
345 };
346
347 wdog1: wdog@403D0000 {
348 compatible = "fsl,imx7ulp-wdt";
349 reg = <0x403D0000 0x10000>;
350 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&clks IMX7ULP_CLK_WDG1>;
352 assigned-clocks = <&clks IMX7ULP_CLK_WDG1>;
353 assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
354 /*
355 * As the 1KHz LPO clock rate is not trimed,the actually clock
356 * is about 667Hz, so the init timeout 60s should set 40*1000
357 * in the TOVAL register.
358 */
359 timeout-sec = <40>;
360 };
361
362 wdog2: wdog@40430000 {
363 compatible = "fsl,imx7ulp-wdt";
364 reg = <0x40430000 0x10000>;
365 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&clks IMX7ULP_CLK_WDG2>;
367 assigned-clocks = <&clks IMX7ULP_CLK_WDG2>;
368 assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
369 timeout-sec = <40>;
370 };
371
372 clks: scg1@403E0000 {
373 compatible = "fsl,imx7ulp-scg1";
374 reg = <0x403E0000 0x10000>;
375 clocks = <&ckil>, <&osc>, <&sirc>,
376 <&firc>, <&upll>, <&mpll>;
377 clock-names = "ckil", "osc", "sirc",
378 "firc", "upll", "mpll";
379 #clock-cells = <1>;
380 assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
381 <&clks IMX7ULP_CLK_USDHC1>;
382 assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
383 <&clks IMX7ULP_CLK_NIC1_DIV>;
384 };
385
386 pcc2: pcc2@403F0000 {
387 compatible = "fsl,imx7ulp-pcc2";
388 reg = <0x403F0000 0x10000>;
389 };
390
391 pmc1: pmc1@40400000 {
392 compatible = "fsl,imx7ulp-pmc1";
393 reg = <0x40400000 0x1000>;
394 };
395
396 smc1: smc1@40410000 {
397 compatible = "fsl,imx7ulp-smc1";
398 reg = <0x40410000 0x1000>;
399 };
400
401 };
402
403 ahbbridge1: ahb-bridge1@40800000 {
404 compatible = "fsl,aips-bus", "simple-bus";
405 #address-cells = <1>;
406 #size-cells = <1>;
407 reg = <0x40800000 0x800000>;
408 ranges;
409
410 lpi2c6: lpi2c6@40A40000 {
411 compatible = "fsl,imx7ulp-lpi2c";
412 reg = <0x40A40000 0x10000>;
413 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&clks IMX7ULP_CLK_LPI2C6>;
415 clock-names = "ipg";
416 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>;
417 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
418 assigned-clock-rates = <48000000>;
419 status = "disabled";
420 };
421
422 lpi2c7: lpi2c7@40A50000 {
423 compatible = "fsl,imx7ulp-lpi2c";
424 reg = <0x40A50000 0x10000>;
425 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clks IMX7ULP_CLK_LPI2C7>;
427 clock-names = "ipg";
428 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>;
429 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
430 assigned-clock-rates = <48000000>;
431 status = "disabled";
432 };
433
434 lpuart6: serial@40A60000 {
435 compatible = "fsl,imx7ulp-lpuart";
436 reg = <0x40A60000 0x1000>;
437 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&clks IMX7ULP_CLK_LPUART6>;
439 clock-names = "ipg";
440 assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>;
441 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
442 assigned-clock-rates = <48000000>;
443 dmas = <&edma0 0 22>, <&edma0 0 21>;
444 dma-names = "tx","rx";
445 status = "disabled";
446 };
447
448 lpuart7: serial@40A70000 {
449 compatible = "fsl,imx7ulp-lpuart";
450 reg = <0x40A70000 0x1000>;
451 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&clks IMX7ULP_CLK_LPUART7>;
453 clock-names = "ipg";
454 assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>;
455 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
456 assigned-clock-rates = <50000000>;
457 dmas = <&edma0 0 24>, <&edma0 0 23>;
458 dma-names = "tx","rx";
459 status = "disabled";
460 };
461
462 lcdif: lcdif@40AA0000 {
463 compatible = "fsl,imx7ulp-lcdif";
464 reg = <0x40aa0000 0x10000>;
465 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clks IMX7ULP_CLK_DUMMY>,
467 <&clks IMX7ULP_CLK_LCDIF>,
468 <&clks IMX7ULP_CLK_DUMMY>;
469 clock-names = "axi", "pix", "disp_axi";
470 status = "disabled";
471 };
472
473 mipi_dsi: mipi_dsi@40A90000 {
474 compatible = "fsl,imx7ulp-mipi-dsi";
475 reg = <0x40A90000 0x10000>;
476 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&clks IMX7ULP_CLK_DSI>;
478 clock-names = "mipi_dsi_clk";
479 sim = <&sim>;
480 status = "disabled";
481 };
482
483 mmdc: mmdc@40ab0000 {
484 compatible = "fsl,imx7ulp-mmdc";
485 reg = <0x40ab0000 0x4000>;
486 };
487
488 pcc3: pcc3@40B30000 {
489 compatible = "fsl,imx7ulp-pcc3";
490 reg = <0x40B30000 0x10000>;
491 };
492
493 iomuxc: iomuxc@4103D000 {
494 compatible = "fsl,imx7ulp-iomuxc-0";
495 reg = <0x4103D000 0x1000>;
496 fsl,mux_mask = <0xf00>;
497 status = "disabled";
498 };
499
500 iomuxc1: iomuxc1@40ac0000 {
501 compatible = "fsl,imx7ulp-iomuxc-1";
502 reg = <0x40ac0000 0x1000>;
503 fsl,mux_mask = <0xf00>;
504 };
505
506 gpio0: gpio@40ae0000 {
507 compatible = "fsl,imx7ulp-gpio";
508 reg = <0x40ae0000 0x1000 0x400F0000 0x40>;
509 gpio-controller;
510 #gpio-cells = <2>;
511 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
512 interrupt-controller;
513 #interrupt-cells = <2>;
514 gpio-ranges = <&iomuxc1 0 0 32>;
515 };
516
517 gpio1: gpio@40af0000 {
518 compatible = "fsl,imx7ulp-gpio";
519 reg = <0x40af0000 0x1000 0x400F0040 0x40>;
520 gpio-controller;
521 #gpio-cells = <2>;
522 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
523 interrupt-controller;
524 #interrupt-cells = <2>;
525 gpio-ranges = <&iomuxc1 0 32 32>;
526 };
527
528 gpio2: gpio@40b00000 {
529 compatible = "fsl,imx7ulp-gpio";
530 reg = <0x40b00000 0x1000 0x400F0080 0x40>;
531 gpio-controller;
532 #gpio-cells = <2>;
533 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
534 interrupt-controller;
535 #interrupt-cells = <2>;
536 gpio-ranges = <&iomuxc1 0 64 32>;
537 };
538
539 gpio3: gpio@40b10000 {
540 compatible = "fsl,imx7ulp-gpio";
541 reg = <0x40b10000 0x1000 0x400F00c0 0x40>;
542 gpio-controller;
543 #gpio-cells = <2>;
544 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
547 gpio-ranges = <&iomuxc1 0 96 32>;
548 };
549
550 pmc0: pmc0@410a1000 {
551 compatible = "fsl,imx7ulp-pmc0";
552 reg = <0x410a1000 0x1000>;
553 };
554
555 sim: sim@410a3000 {
556 compatible = "fsl,imx7ulp-sim", "syscon";
557 reg = <0x410a3000 0x1000>;
558 };
559
560 qspi1: qspi@410A5000 {
561 #address-cells = <1>;
562 #size-cells = <0>;
563 compatible = "fsl,imx7ulp-qspi";
564 reg = <0x410A5000 0x10000>, <0xC0000000 0x10000000>;
565 reg-names = "QuadSPI", "QuadSPI-memory";
566 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&clks IMX7ULP_CLK_DUMMY>,
568 <&clks IMX7ULP_CLK_DUMMY>;
569 clock-names = "qspi_en", "qspi";
570 status = "disabled";
571 };
572
573 gpu: gpu@41800000 {
574 compatible = "fsl,imx6q-gpu";
575 reg = <0x41800000 0x80000>, <0x41880000 0x80000>,
576 <0x60000000 0x40000000>, <0x0 0x4000000>;
577 reg-names = "iobase_3d", "iobase_2d",
578 "phys_baseaddr", "contiguous_mem";
579 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "irq_3d", "irq_2d";
582 clocks = <&clks IMX7ULP_CLK_GPU3D>,
583 <&clks IMX7ULP_CLK_NIC1_DIV>,
584 <&clks IMX7ULP_CLK_GPU_DIV>,
585 <&clks IMX7ULP_CLK_GPU2D>,
586 <&clks IMX7ULP_CLK_NIC1_DIV>,
587 <&clks IMX7ULP_CLK_NIC1_DIV>;
588 clock-names = "gpu3d_clk", "gpu3d_shader_clk",
589 "gpu3d_axi_clk", "gpu2d_clk",
590 "gpu2d_shader_clk", "gpu2d_axi_clk";
591 };
592 };
593
594 imx_ion {
595 compatible = "fsl,mxc-ion";
596 fsl,heap-id = <0>;
597 };
598};