blob: 42d65d356dac55a03a194c95ea5879c6c15e4f2b [file] [log] [blame]
Nobuhiro Iwamatsuc6ccb472013-11-21 17:06:45 +09001/*
2 * arch/arm/include/asm/arch-rmobile/r8a7790.h
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9#ifndef __ASM_ARCH_R8A7790_H
10#define __ASM_ARCH_R8A7790_H
11
12/*
13 * R8A7790 I/O Addresses
14 */
15#define RWDT_BASE 0xE6020000
16#define SWDT_BASE 0xE6030000
17#define LBSC_BASE 0xFEC00200
18#define DBSC3_0_BASE 0xE6790000
19#define DBSC3_1_BASE 0xE67A0000
20#define TMU_BASE 0xE61E0000
21#define GPIO5_BASE 0xE6055000
22
23#define S3C_BASE 0xE6784000
24#define S3C_INT_BASE 0xE6784A00
25#define S3C_MEDIA_BASE 0xE6784B00
26
27#define S3C_QOS_DCACHE_BASE 0xE6784BDC
28#define S3C_QOS_CCI0_BASE 0xE6784C00
29#define S3C_QOS_CCI1_BASE 0xE6784C24
30#define S3C_QOS_MXI_BASE 0xE6784C48
31#define S3C_QOS_AXI_BASE 0xE6784C6C
32
33#define DBSC3_0_QOS_R0_BASE 0xE6791000
34#define DBSC3_0_QOS_R1_BASE 0xE6791100
35#define DBSC3_0_QOS_R2_BASE 0xE6791200
36#define DBSC3_0_QOS_R3_BASE 0xE6791300
37#define DBSC3_0_QOS_R4_BASE 0xE6791400
38#define DBSC3_0_QOS_R5_BASE 0xE6791500
39#define DBSC3_0_QOS_R6_BASE 0xE6791600
40#define DBSC3_0_QOS_R7_BASE 0xE6791700
41#define DBSC3_0_QOS_R8_BASE 0xE6791800
42#define DBSC3_0_QOS_R9_BASE 0xE6791900
43#define DBSC3_0_QOS_R10_BASE 0xE6791A00
44#define DBSC3_0_QOS_R11_BASE 0xE6791B00
45#define DBSC3_0_QOS_R12_BASE 0xE6791C00
46#define DBSC3_0_QOS_R13_BASE 0xE6791D00
47#define DBSC3_0_QOS_R14_BASE 0xE6791E00
48#define DBSC3_0_QOS_R15_BASE 0xE6791F00
49#define DBSC3_0_QOS_W0_BASE 0xE6792000
50#define DBSC3_0_QOS_W1_BASE 0xE6792100
51#define DBSC3_0_QOS_W2_BASE 0xE6792200
52#define DBSC3_0_QOS_W3_BASE 0xE6792300
53#define DBSC3_0_QOS_W4_BASE 0xE6792400
54#define DBSC3_0_QOS_W5_BASE 0xE6792500
55#define DBSC3_0_QOS_W6_BASE 0xE6792600
56#define DBSC3_0_QOS_W7_BASE 0xE6792700
57#define DBSC3_0_QOS_W8_BASE 0xE6792800
58#define DBSC3_0_QOS_W9_BASE 0xE6792900
59#define DBSC3_0_QOS_W10_BASE 0xE6792A00
60#define DBSC3_0_QOS_W11_BASE 0xE6792B00
61#define DBSC3_0_QOS_W12_BASE 0xE6792C00
62#define DBSC3_0_QOS_W13_BASE 0xE6792D00
63#define DBSC3_0_QOS_W14_BASE 0xE6792E00
64#define DBSC3_0_QOS_W15_BASE 0xE6792F00
65
66#define DBSC3_0_DBADJ2 0xE67900C8
67
68#define CCI_400_MAXOT_1 0xF0091110
69#define CCI_400_MAXOT_2 0xF0092110
70#define CCI_400_QOSCNTL_1 0xF009110C
71#define CCI_400_QOSCNTL_2 0xF009210C
72
73#define MXI_BASE 0xFE960000
74#define MXI_QOS_BASE 0xFE960300
75
76#define SYS_AXI_SYX64TO128_BASE 0xFF800300
77#define SYS_AXI_AVB_BASE 0xFF800340
78#define SYS_AXI_G2D_BASE 0xFF800540
79#define SYS_AXI_IMP0_BASE 0xFF800580
80#define SYS_AXI_IMP1_BASE 0xFF8005C0
81#define SYS_AXI_IMUX0_BASE 0xFF800600
82#define SYS_AXI_IMUX1_BASE 0xFF800640
83#define SYS_AXI_IMUX2_BASE 0xFF800680
84#define SYS_AXI_LBS_BASE 0xFF8006C0
85#define SYS_AXI_MMUDS_BASE 0xFF800700
86#define SYS_AXI_MMUM_BASE 0xFF800740
87#define SYS_AXI_MMUR_BASE 0xFF800780
88#define SYS_AXI_MMUS0_BASE 0xFF8007C0
89#define SYS_AXI_MMUS1_BASE 0xFF800800
90#define SYS_AXI_MTSB0_BASE 0xFF800880
91#define SYS_AXI_MTSB1_BASE 0xFF8008C0
92#define SYS_AXI_PCI_BASE 0xFF800900
93#define SYS_AXI_RTX_BASE 0xFF800940
94#define SYS_AXI_SDS0_BASE 0xFF800A80
95#define SYS_AXI_SDS1_BASE 0xFF800AC0
96#define SYS_AXI_USB20_BASE 0xFF800C00
97#define SYS_AXI_USB21_BASE 0xFF800C40
98#define SYS_AXI_USB22_BASE 0xFF800C80
99#define SYS_AXI_USB30_BASE 0xFF800CC0
100
101#define RT_AXI_SHX_BASE 0xFF810100
102#define RT_AXI_RDS_BASE 0xFF8101C0
103#define RT_AXI_RTX64TO128_BASE 0xFF810200
104#define RT_AXI_STPRO_BASE 0xFF810240
105
106#define MP_AXI_ADSP_BASE 0xFF820100
107#define MP_AXI_ASDS0_BASE 0xFF8201C0
108#define MP_AXI_ASDS1_BASE 0xFF820200
109#define MP_AXI_MLP_BASE 0xFF820240
110#define MP_AXI_MMUMP_BASE 0xFF820280
111#define MP_AXI_SPU_BASE 0xFF8202C0
112#define MP_AXI_SPUC_BASE 0xFF820300
113
114#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
115#define SYS_AXI256_SYX_BASE 0xFF860140
116#define SYS_AXI256_MPX_BASE 0xFF860180
117#define SYS_AXI256_MXI_BASE 0xFF8601C0
118
119#define CCI_AXI_MMUS0_BASE 0xFF880100
120#define CCI_AXI_SYX2_BASE 0xFF880140
121#define CCI_AXI_MMUR_BASE 0xFF880180
122#define CCI_AXI_MMUDS_BASE 0xFF8801C0
123#define CCI_AXI_MMUM_BASE 0xFF880200
124#define CCI_AXI_MXI_BASE 0xFF880240
125#define CCI_AXI_MMUS1_BASE 0xFF880280
126#define CCI_AXI_MMUMP_BASE 0xFF8802C0
127
128#define MEDIA_AXI_JPR_BASE 0xFE964100
129#define MEDIA_AXI_JPW_BASE 0xFE966100
130#define MEDIA_AXI_GCU0R_BASE 0xFE964140
131#define MEDIA_AXI_GCU0W_BASE 0xFE966140
132#define MEDIA_AXI_GCU1R_BASE 0xFE964180
133#define MEDIA_AXI_GCU1W_BASE 0xFE966180
134#define MEDIA_AXI_TDMR_BASE 0xFE964500
135#define MEDIA_AXI_TDMW_BASE 0xFE966500
136#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
137#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
138#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
139#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
140#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
141#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
142#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
143#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
144#define MEDIA_AXI_VIN0W_BASE 0xFE966900
145#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
146#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
147#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
148#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
149#define MEDIA_AXI_IMSR_BASE 0xFE964D80
150#define MEDIA_AXI_IMSW_BASE 0xFE966D80
151#define MEDIA_AXI_VSP1R_BASE 0xFE965100
152#define MEDIA_AXI_VSP1W_BASE 0xFE967100
153#define MEDIA_AXI_FDP1R_BASE 0xFE965140
154#define MEDIA_AXI_FDP1W_BASE 0xFE967140
155#define MEDIA_AXI_IMRR_BASE 0xFE965180
156#define MEDIA_AXI_IMRW_BASE 0xFE967180
157#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
158#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
159#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
160#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
161#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
162#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
163#define MEDIA_AXI_DU0R_BASE 0xFE965580
164#define MEDIA_AXI_DU0W_BASE 0xFE967580
165#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
166#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
167#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
168#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
169#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
170#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
171#define MEDIA_AXI_VPC0R_BASE 0xFE965980
172#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
173#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
174#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
175#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
176#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
177
178#define SYS_AXI_AVBDMSCR 0xFF802000
179#define SYS_AXI_SYX2DMSCR 0xFF802004
180#define SYS_AXI_CC50DMSCR 0xFF802008
181#define SYS_AXI_CC51DMSCR 0xFF80200C
182#define SYS_AXI_CCIDMSCR 0xFF802010
183#define SYS_AXI_CSDMSCR 0xFF802014
184#define SYS_AXI_DDMDMSCR 0xFF802018
185#define SYS_AXI_ETHDMSCR 0xFF80201C
186#define SYS_AXI_G2DDMSCR 0xFF802020
187#define SYS_AXI_IMP0DMSCR 0xFF802024
188#define SYS_AXI_IMP1DMSCR 0xFF802028
189#define SYS_AXI_LBSDMSCR 0xFF80202C
190#define SYS_AXI_MMUDSDMSCR 0xFF802030
191#define SYS_AXI_MMUMXDMSCR 0xFF802034
192#define SYS_AXI_MMURDDMSCR 0xFF802038
193#define SYS_AXI_MMUS0DMSCR 0xFF80203C
194#define SYS_AXI_MMUS1DMSCR 0xFF802040
195#define SYS_AXI_MPXDMSCR 0xFF802044
196#define SYS_AXI_MTSB0DMSCR 0xFF802048
197#define SYS_AXI_MTSB1DMSCR 0xFF80204C
198#define SYS_AXI_PCIDMSCR 0xFF802050
199#define SYS_AXI_RTXDMSCR 0xFF802054
200#define SYS_AXI_SAT0DMSCR 0xFF802058
201#define SYS_AXI_SAT1DMSCR 0xFF80205C
202#define SYS_AXI_SDM0DMSCR 0xFF802060
203#define SYS_AXI_SDM1DMSCR 0xFF802064
204#define SYS_AXI_SDS0DMSCR 0xFF802068
205#define SYS_AXI_SDS1DMSCR 0xFF80206C
206#define SYS_AXI_ETRABDMSCR 0xFF802070
207#define SYS_AXI_ETRKFDMSCR 0xFF802074
208#define SYS_AXI_UDM0DMSCR 0xFF802078
209#define SYS_AXI_UDM1DMSCR 0xFF80207C
210#define SYS_AXI_USB20DMSCR 0xFF802080
211#define SYS_AXI_USB21DMSCR 0xFF802084
212#define SYS_AXI_USB22DMSCR 0xFF802088
213#define SYS_AXI_USB30DMSCR 0xFF80208C
214#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
215#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
216#define SYS_AXI_AVBSLVDMSCR 0xFF802108
217#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
218#define SYS_AXI_ETHSLVDMSCR 0xFF802110
219#define SYS_AXI_GICSLVDMSCR 0xFF802114
220#define SYS_AXI_IMPSLVDMSCR 0xFF802118
221#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
222#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
223#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
224#define SYS_AXI_LBSSLVDMSCR 0xFF802128
225#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
226#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
227#define SYS_AXI_MPXSLVDMSCR 0xFF802134
228#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
229#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
230#define SYS_AXI_MXTSLVDMSCR 0xFF802140
231#define SYS_AXI_PCISLVDMSCR 0xFF802144
232#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
233#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
234#define SYS_AXI_RTXSLVDMSCR 0xFF802150
235#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
236#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
237#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
238#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
239#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
240#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
241#define SYS_AXI_SGXSLVDMSCR 0xFF802180
242#define SYS_AXI_STBSLVDMSCR 0xFF802188
243#define SYS_AXI_STMSLVDMSCR 0xFF80218C
244#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
245#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
246#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
247#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
248#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
249#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
250#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
251
252#define RT_AXI_CBMDMSCR 0xFF812000
253#define RT_AXI_DBDMSCR 0xFF812004
254#define RT_AXI_RDMDMSCR 0xFF812008
255#define RT_AXI_RDSDMSCR 0xFF81200C
256#define RT_AXI_STRDMSCR 0xFF812010
257#define RT_AXI_SY2RTDMSCR 0xFF812014
258#define RT_AXI_CBSSLVDMSCR 0xFF812100
259#define RT_AXI_DBSSLVDMSCR 0xFF812104
260#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
261#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
262#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
263#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
264#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
265#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
266#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
267#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
268
269#define MP_AXI_ADSPDMSCR 0xFF822000
270#define MP_AXI_ASDM0DMSCR 0xFF822004
271#define MP_AXI_ASDM1DMSCR 0xFF822008
272#define MP_AXI_ASDS0DMSCR 0xFF82200C
273#define MP_AXI_ASDS1DMSCR 0xFF822010
274#define MP_AXI_MLPDMSCR 0xFF822014
275#define MP_AXI_MMUMPDMSCR 0xFF822018
276#define MP_AXI_SPUDMSCR 0xFF82201C
277#define MP_AXI_SPUCDMSCR 0xFF822020
278#define MP_AXI_SY2MPDMSCR 0xFF822024
279#define MP_AXI_ADSPSLVDMSCR 0xFF822100
280#define MP_AXI_MLMSLVDMSCR 0xFF822104
281#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
282#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
283#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
284#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
285#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
286#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
287#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
288#define MP_AXI_SPUSLVDMSCR 0xFF822128
289#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
290
291#define ADM_AXI_ASDM0DMSCR 0xFF842000
292#define ADM_AXI_ASDM1DMSCR 0xFF842004
293#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
294#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
295#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
296
297#define DM_AXI_RDMDMSCR 0xFF852000
298#define DM_AXI_SDM0DMSCR 0xFF852004
299#define DM_AXI_SDM1DMSCR 0xFF852008
300#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
301#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
302#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
303#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
304#define DM_AXI_RAP5SLVDMSCR 0xFF852110
305#define DM_AXI_SAP4SLVDMSCR 0xFF852114
306#define DM_AXI_SAP5SLVDMSCR 0xFF852118
307#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
308#define DM_AXI_SAP65SLVDMSCR 0xFF852120
309#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
310#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
311#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
312#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
313
314#define SYS_AXI256_SYXDMSCR 0xFF862000
315#define SYS_AXI256_MPXDMSCR 0xFF862004
316#define SYS_AXI256_MXIDMSCR 0xFF862008
317#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
318#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
319#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
320#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
321#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
322
323#define MXT_SYXDMSCR 0xFF872000
324#define MXT_CMM0SLVDMSCR 0xFF872100
325#define MXT_CMM1SLVDMSCR 0xFF872104
326#define MXT_CMM2SLVDMSCR 0xFF872108
327#define MXT_FDPSLVDMSCR 0xFF87210C
328#define MXT_IMRSLVDMSCR 0xFF872110
329#define MXT_VINSLVDMSCR 0xFF872114
330#define MXT_VPC0SLVDMSCR 0xFF872118
331#define MXT_VPC1SLVDMSCR 0xFF87211C
332#define MXT_VSP0SLVDMSCR 0xFF872120
333#define MXT_VSP1SLVDMSCR 0xFF872124
334#define MXT_VSPD0SLVDMSCR 0xFF872128
335#define MXT_VSPD1SLVDMSCR 0xFF87212C
336#define MXT_MAP1SLVDMSCR 0xFF872130
337#define MXT_MAP2SLVDMSCR 0xFF872134
338
339#define CCI_AXI_MMUS0DMSCR 0xFF882000
340#define CCI_AXI_SYX2DMSCR 0xFF882004
341#define CCI_AXI_MMURDMSCR 0xFF882008
342#define CCI_AXI_MMUDSDMSCR 0xFF88200C
343#define CCI_AXI_MMUMDMSCR 0xFF882010
344#define CCI_AXI_MXIDMSCR 0xFF882014
345#define CCI_AXI_MMUS1DMSCR 0xFF882018
346#define CCI_AXI_MMUMPDMSCR 0xFF88201C
347#define CCI_AXI_DVMDMSCR 0xFF882020
348#define CCI_AXI_CCISLVDMSCR 0xFF882100
349
350#define CCI_AXI_IPMMUIDVMCR 0xFF880400
351#define CCI_AXI_IPMMURDVMCR 0xFF880404
352#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
353#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
354#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
355#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
356#define CCI_AXI_AX2ADDRMASK 0xFF88041C
357
358#ifndef __ASSEMBLY__
359#include <asm/types.h>
360
361/* RWDT */
362struct r8a7790_rwdt {
363 u32 rwtcnt; /* 0x00 */
364 u32 rwtcsra; /* 0x04 */
365 u16 rwtcsrb; /* 0x08 */
366};
367
368/* SWDT */
369struct r8a7790_swdt {
370 u32 swtcnt; /* 0x00 */
371 u32 swtcsra; /* 0x04 */
372 u16 swtcsrb; /* 0x08 */
373};
374
375/* LBSC */
376struct r8a7790_lbsc {
377 u32 cs0ctrl;
378 u32 cs1ctrl;
379 u32 ecs0ctrl;
380 u32 ecs1ctrl;
381 u32 ecs2ctrl;
382 u32 ecs3ctrl;
383 u32 ecs4ctrl;
384 u32 ecs5ctrl;
385 u32 dummy0[4]; /* 0x20 .. 0x2C */
386 u32 cswcr0;
387 u32 cswcr1;
388 u32 ecswcr0;
389 u32 ecswcr1;
390 u32 ecswcr2;
391 u32 ecswcr3;
392 u32 ecswcr4;
393 u32 ecswcr5;
394 u32 exdmawcr0;
395 u32 exdmawcr1;
396 u32 exdmawcr2;
397 u32 dummy1[9]; /* 0x5C .. 0x7C */
398 u32 cspwcr0;
399 u32 cspwcr1;
400 u32 ecspwcr0;
401 u32 ecspwcr1;
402 u32 ecspwcr2;
403 u32 ecspwcr3;
404 u32 ecspwcr4;
405 u32 ecspwcr5;
406 u32 exwtsync;
407 u32 dummy2[3]; /* 0xA4 .. 0xAC */
408 u32 cs0bstctl;
409 u32 cs0btph;
410 u32 dummy3[2]; /* 0xB8 .. 0xBC */
411 u32 cs1gdst;
412 u32 ecs0gdst;
413 u32 ecs1gdst;
414 u32 ecs2gdst;
415 u32 ecs3gdst;
416 u32 ecs4gdst;
417 u32 ecs5gdst;
418 u32 dummy4[5]; /* 0xDC .. 0xEC */
419 u32 exdmaset0;
420 u32 exdmaset1;
421 u32 exdmaset2;
422 u32 dummy5[5]; /* 0xFC .. 0x10C */
423 u32 exdmcr0;
424 u32 exdmcr1;
425 u32 exdmcr2;
426 u32 dummy6[5]; /* 0x11C .. 0x12C */
427 u32 bcintsr;
428 u32 bcintcr;
429 u32 bcintmr;
430 u32 dummy7; /* 0x13C */
431 u32 exbatlv;
432 u32 exwtsts;
433 u32 dummy8[14]; /* 0x148 .. 0x17C */
434 u32 atacsctrl;
435 u32 dummy9[15]; /* 0x184 .. 0x1BC */
436 u32 exbct;
437 u32 extct;
438};
439
440/* DBSC3 */
441struct r8a7790_dbsc3 {
442 u32 dummy0[3]; /* 0x00 .. 0x08 */
443 u32 dbstate1;
444 u32 dbacen;
445 u32 dbrfen;
446 u32 dbcmd;
447 u32 dbwait;
448 u32 dbkind;
449 u32 dbconf0;
450 u32 dummy1[2]; /* 0x28 .. 0x2C */
451 u32 dbphytype;
452 u32 dummy2[3]; /* 0x34 .. 0x3C */
453 u32 dbtr0;
454 u32 dbtr1;
455 u32 dbtr2;
456 u32 dummy3; /* 0x4C */
457 u32 dbtr3;
458 u32 dbtr4;
459 u32 dbtr5;
460 u32 dbtr6;
461 u32 dbtr7;
462 u32 dbtr8;
463 u32 dbtr9;
464 u32 dbtr10;
465 u32 dbtr11;
466 u32 dbtr12;
467 u32 dbtr13;
468 u32 dbtr14;
469 u32 dbtr15;
470 u32 dbtr16;
471 u32 dbtr17;
472 u32 dbtr18;
473 u32 dbtr19;
474 u32 dummy4[7]; /* 0x94 .. 0xAC */
475 u32 dbbl;
476 u32 dummy5[3]; /* 0xB4 .. 0xBC */
477 u32 dbadj0;
478 u32 dummy6; /* 0xC4 */
479 u32 dbadj2;
480 u32 dummy7[5]; /* 0xCC .. 0xDC */
481 u32 dbrfcnf0;
482 u32 dbrfcnf1;
483 u32 dbrfcnf2;
484 u32 dummy8[2]; /* 0xEC .. 0xF0 */
485 u32 dbcalcnf;
486 u32 dbcaltr;
487 u32 dummy9; /* 0xFC */
488 u32 dbrnk0;
489 u32 dummy10[31]; /* 0x104 .. 0x17C */
490 u32 dbpdncnf;
491 u32 dummy11[47]; /* 0x184 ..0x23C */
492 u32 dbdfistat;
493 u32 dbdficnt;
494 u32 dummy12[14]; /* 0x248 .. 0x27C */
495 u32 dbpdlck;
496 u32 dummy13[3]; /* 0x284 .. 0x28C */
497 u32 dbpdrga;
498 u32 dummy14[3]; /* 0x294 .. 0x29C */
499 u32 dbpdrgd;
500 u32 dummy15[24]; /* 0x2A4 .. 0x300 */
501 u32 dbbs0cnt1;
502 u32 dummy16[30]; /* 0x308 .. 0x37C */
503 u32 dbwt0cnf0;
504 u32 dbwt0cnf1;
505 u32 dbwt0cnf2;
506 u32 dbwt0cnf3;
507 u32 dbwt0cnf4;
508};
509
510/* GPIO */
511struct r8a7790_gpio {
512 u32 iointsel;
513 u32 inoutsel;
514 u32 outdt;
515 u32 indt;
516 u32 intdt;
517 u32 intclr;
518 u32 intmsk;
519 u32 posneg;
520 u32 edglevel;
521 u32 filonoff;
522 u32 intmsks;
523 u32 mskclrs;
524 u32 outdtsel;
525 u32 outdth;
526 u32 outdtl;
527 u32 bothedge;
528};
529
530/* S3C(QoS) */
531struct r8a7790_s3c {
532 u32 s3cexcladdmsk;
533 u32 s3cexclidmsk;
534 u32 s3cadsplcr;
535 u32 s3cmaar;
536 u32 s3carcr11;
537 u32 s3crorr;
538 u32 s3cworr;
539 u32 s3carcr22;
540 u32 dummy1[2]; /* 0x20 .. 0x24 */
541 u32 s3cmctr;
542 u32 dummy2; /* 0x2C */
543 u32 cconf0;
544 u32 cconf1;
545 u32 cconf2;
546 u32 cconf3;
547};
548
549struct r8a7790_s3c_qos {
550 u32 s3cqos0;
551 u32 s3cqos1;
552 u32 s3cqos2;
553 u32 s3cqos3;
554 u32 s3cqos4;
555 u32 s3cqos5;
556 u32 s3cqos6;
557 u32 s3cqos7;
558 u32 s3cqos8;
559};
560
561/* DBSC(QoS) */
562struct r8a7790_dbsc3_qos {
563 u32 dblgcnt;
564 u32 dbtmval0;
565 u32 dbtmval1;
566 u32 dbtmval2;
567 u32 dbtmval3;
568 u32 dbrqctr;
569 u32 dbthres0;
570 u32 dbthres1;
571 u32 dbthres2;
572 u32 dummy0; /* 0x24 */
573 u32 dblgqon;
574};
575
576/* MXI(QoS) */
577struct r8a7790_mxi {
578 u32 mxsaar0;
579 u32 mxsaar1;
580 u32 dummy0[7]; /* 0x08 .. 0x20 */
581 u32 mxaxiracr;
582 u32 mxs3cracr;
583 u32 dummy1[2]; /* 0x2C .. 0x30 */
584 u32 mxaxiwacr;
585 u32 mxs3cwacr;
586 u32 dummy2; /* 0x3C */
587 u32 mxrtcr;
588 u32 mxwtcr;
589};
590
591struct r8a7790_mxi_qos {
592 u32 vspdu0;
593 u32 vspdu1;
594 u32 du0;
595 u32 du1;
596};
597
598/* AXI(QoS) */
599struct r8a7790_axi_qos {
600 u32 qosconf;
601 u32 qosctset0;
602 u32 qosctset1;
603 u32 qosctset2;
604 u32 qosctset3;
605 u32 qosreqctr;
606 u32 qosthres0;
607 u32 qosthres1;
608 u32 qosthres2;
609 u32 qosqon;
610};
611
612#endif
613
614#endif /* __ASM_ARCH_R8A7790_H */