blob: 3d9422d5a219e9e6592210dcb54af078f8903759 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peng Fanfcabb6d2016-01-28 16:55:04 +08002/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
Peng Fanfcabb6d2016-01-28 16:55:04 +08004 */
5
6#include <common.h>
Peng Fand7e46ca2018-01-10 13:20:32 +08007#include <asm/io.h>
Peng Fanbac08452018-01-10 13:20:33 +08008#include <asm/mach-imx/sys_proto.h>
Peng Fanfcabb6d2016-01-28 16:55:04 +08009#include <command.h>
Peng Fanbac08452018-01-10 13:20:33 +080010#include <imx_sip.h>
Tom Rini2f218872018-01-03 08:52:39 -050011#include <linux/compiler.h>
Peng Fanfcabb6d2016-01-28 16:55:04 +080012
Peng Fand7e46ca2018-01-10 13:20:32 +080013int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
Peng Fanfcabb6d2016-01-28 16:55:04 +080014{
Peng Fand7e46ca2018-01-10 13:20:32 +080015 ulong stack, pc;
16
17 if (!boot_private_data)
18 return -EINVAL;
19
Gary Bissond82889d2018-11-14 17:55:29 +010020 stack = *(u32 *)boot_private_data;
21 pc = *(u32 *)(boot_private_data + 4);
Peng Fand7e46ca2018-01-10 13:20:32 +080022
23 /* Set the stack and pc to M4 bootROM */
24 writel(stack, M4_BOOTROM_BASE_ADDR);
25 writel(pc, M4_BOOTROM_BASE_ADDR + 4);
26
27 /* Enable M4 */
Peng Fan39945c12018-11-20 10:19:25 +000028#ifdef CONFIG_IMX8M
Ye Lie5e91092019-10-26 16:24:03 +020029 call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0);
Peng Fanbac08452018-01-10 13:20:33 +080030#else
Peng Fand7e46ca2018-01-10 13:20:32 +080031 clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
32 SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
Peng Fanbac08452018-01-10 13:20:33 +080033#endif
Peng Fand7e46ca2018-01-10 13:20:32 +080034
35 return 0;
Peng Fanfcabb6d2016-01-28 16:55:04 +080036}
37
Peng Fand7e46ca2018-01-10 13:20:32 +080038int arch_auxiliary_core_check_up(u32 core_id)
Peng Fanfcabb6d2016-01-28 16:55:04 +080039{
Peng Fan39945c12018-11-20 10:19:25 +000040#ifdef CONFIG_IMX8M
Ye Lie5e91092019-10-26 16:24:03 +020041 return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0);
Peng Fanbac08452018-01-10 13:20:33 +080042#else
Peng Fand7e46ca2018-01-10 13:20:32 +080043 unsigned int val;
44
45 val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
46
47 if (val & SRC_M4C_NON_SCLR_RST_MASK)
48 return 0; /* assert in reset */
49
50 return 1;
Peng Fanbac08452018-01-10 13:20:33 +080051#endif
Peng Fanfcabb6d2016-01-28 16:55:04 +080052}
53
Peng Fanfcabb6d2016-01-28 16:55:04 +080054/*
55 * To i.MX6SX and i.MX7D, the image supported by bootaux needs
56 * the reset vector at the head for the image, with SP and PC
57 * as the first two words.
58 *
59 * Per the cortex-M reference manual, the reset vector of M4 needs
60 * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
61 * of that vector. So to boot M4, the A core must build the M4's reset
62 * vector with getting the PC and SP from image and filling them to
63 * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
64 * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
65 * accessing the M4 TCMUL.
66 */
Tom Rini2f218872018-01-03 08:52:39 -050067static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Peng Fanfcabb6d2016-01-28 16:55:04 +080068{
69 ulong addr;
70 int ret, up;
71
72 if (argc < 2)
73 return CMD_RET_USAGE;
74
75 up = arch_auxiliary_core_check_up(0);
76 if (up) {
77 printf("## Auxiliary core is already up\n");
78 return CMD_RET_SUCCESS;
79 }
80
81 addr = simple_strtoul(argv[1], NULL, 16);
82
83 printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
84
85 ret = arch_auxiliary_core_up(0, addr);
86 if (ret)
87 return CMD_RET_FAILURE;
88
89 return CMD_RET_SUCCESS;
90}
91
92U_BOOT_CMD(
93 bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
94 "Start auxiliary core",
95 ""
96);