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git01.mediatek.com / filogic / uboot / e5d150ea5d7125e63ade40b219b4a042d21f40d2 / . / arch / sh / include / asm / cpu_sh7750.h
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Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]1/*
2 * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
3 *
Wolfgang Denk0a5c2142007-12-27 01:52:50 +0100[diff] [blame]4 * SH7750/SH7750S/SH7750R/SH7751/SH7751R
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]5 * Internal I/O register
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]8 */
9
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]10#ifndef _ASM_CPU_SH7750_H_
11#define _ASM_CPU_SH7750_H_
12
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]13#ifdef CONFIG_CPU_TYPE_R
14#define CACHE_OC_NUM_WAYS 2
Nobuhiro Iwamatsu53b31432008-03-12 12:10:28 +0900[diff] [blame]15#define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]16#else
17#define CACHE_OC_NUM_WAYS 1
Nobuhiro Iwamatsu53b31432008-03-12 12:10:28 +0900[diff] [blame]18#define CCR_CACHE_INIT 0x0000090B
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]19#endif
20
21/* OCN */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]22#define PTEH 0xFF000000
23#define PTEL 0xFF000004
24#define TTB 0xFF000008
25#define TEA 0xFF00000C
26#define MMUCR 0xFF000010
27#define BASRA 0xFF000014
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]28#define BASRB 0xFF000018
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]29#define CCR 0xFF00001C
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]30#define TRA 0xFF000020
31#define EXPEVT 0xFF000024
32#define INTEVT 0xFF000028
33#define PTEA 0xFF000034
34#define QACR0 0xFF000038
35#define QACR1 0xFF00003C
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]36
37/* UBC */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]38#define BARA 0xFF200000
39#define BAMRA 0xFF200004
40#define BBRA 0xFF200008
41#define BARB 0xFF20000C
42#define BAMRB 0xFF200010
43#define BBRB 0xFF200014
44#define BDRB 0xFF200018
45#define BDMRB 0xFF20001C
46#define BRCR 0xFF200020
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]47
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]48/* BSC */
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]49#define BCR1 0xFF800000
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]50#define BCR2 0xFF800004
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]51#define BCR3 0xFF800050
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]52#define BCR4 0xFE0A00F0
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]53#define WCR1 0xFF800008
54#define WCR2 0xFF80000C
55#define WCR3 0xFF800010
56#define MCR 0xFF800014
57#define PCR 0xFF800018
58#define RTCSR 0xFF80001C
59#define RTCNT 0xFF800020
60#define RTCOR 0xFF800024
61#define RFCR 0xFF800028
62#define PCTRA 0xFF80002C
63#define PDTRA 0xFF800030
64#define PCTRB 0xFF800040
65#define PDTRB 0xFF800044
66#define GPIOIC 0xFF800048
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]67
68/* DMAC */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]69#define SAR0 0xFFA00000
70#define DAR0 0xFFA00004
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]71#define DMATCR0 0xFFA00008
72#define CHCR0 0xFFA0000C
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]73#define SAR1 0xFFA00010
74#define DAR1 0xFFA00014
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]75#define DMATCR1 0xFFA00018
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]76#define CHCR1 0xFFA0001C
77#define SAR2 0xFFA00020
78#define DAR2 0xFFA00024
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]79#define DMATCR2 0xFFA00028
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]80#define CHCR2 0xFFA0002C
81#define SAR3 0xFFA00030
82#define DAR3 0xFFA00034
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]83#define DMATCR3 0xFFA00038
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]84#define CHCR3 0xFFA0003C
85#define DMAOR 0xFFA00040
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]86#define SAR4 0xFFA00050
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]87#define DAR4 0xFFA00054
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]88#define DMATCR4 0xFFA00058
89
90/* CPG */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]91#define FRQCR 0xFFC00000
92#define STBCR 0xFFC00004
93#define WTCNT 0xFFC00008
94#define WTCSR 0xFFC0000C
95#define STBCR2 0xFFC00010
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]96
97/* RTC */
98#define R64CNT 0xFFC80000
99#define RSECCNT 0xFFC80004
100#define RMINCNT 0xFFC80008
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]101#define RHRCNT 0xFFC8000C
102#define RWKCNT 0xFFC80010
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]103#define RDAYCNT 0xFFC80014
104#define RMONCNT 0xFFC80018
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]105#define RYRCNT 0xFFC8001C
106#define RSECAR 0xFFC80020
107#define RMINAR 0xFFC80024
108#define RHRAR 0xFFC80028
109#define RWKAR 0xFFC8002C
110#define RDAYAR 0xFFC80030
111#define RMONAR 0xFFC80034
112#define RCR1 0xFFC80038
113#define RCR2 0xFFC8003C
114#define RCR3 0xFFC80050
115#define RYRAR 0xFFC80054
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]116
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]117/* ICR */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]118#define ICR 0xFFD00000
119#define IPRA 0xFFD00004
120#define IPRB 0xFFD00008
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]121#define IPRC 0xFFD0000C
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]122#define IPRD 0xFFD00010
123#define INTPRI 0xFE080000
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]124#define INTREQ 0xFE080020
125#define INTMSK 0xFE080040
126#define INTMSKCL 0xFE080060
127
128/* CPG */
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]129#define CLKSTP 0xFE0A0000
130#define CLKSTPCLR 0xFE0A0008
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]131
132/* TMU */
Nobuhiro Iwamatsue763f1a2012-08-21 13:14:46 +0900[diff] [blame]133#define TMU_BASE 0xFFD80000
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]134
135/* SCI */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]136#define SCSMR1 0xFFE00000
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]137#define SCF0_BASE SCSMR1
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]138
139/* SCIF */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]140#define SCSMR2 0xFFE80000
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]141#define SCIF1_BASE SCSMR2
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]142
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]143/* H-UDI */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]144#define SDIR 0xFFF00000
145#define SDDR 0xFFF00008
146#define SDINT 0xFFF00014
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900[diff] [blame]147
Nobuhiro Iwamatsu547b67f2007-09-23 02:12:30 +0900[diff] [blame]148#endif /* _ASM_CPU_SH7750_H_ */