Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 2 | /* |
| 3 | * board.c |
| 4 | * |
| 5 | * Board functions for TCL SL50 board |
| 6 | * |
| 7 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
Simon Glass | 79fd214 | 2019-08-01 09:46:43 -0600 | [diff] [blame] | 11 | #include <env.h> |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 12 | #include <errno.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 13 | #include <init.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 14 | #include <net.h> |
Simon Glass | 3673618 | 2019-11-14 12:57:24 -0700 | [diff] [blame] | 15 | #include <serial.h> |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 16 | #include <spl.h> |
| 17 | #include <asm/arch/cpu.h> |
| 18 | #include <asm/arch/hardware.h> |
| 19 | #include <asm/arch/omap.h> |
| 20 | #include <asm/arch/ddr_defs.h> |
| 21 | #include <asm/arch/clock.h> |
| 22 | #include <asm/arch/gpio.h> |
| 23 | #include <asm/arch/mmc_host_def.h> |
| 24 | #include <asm/arch/sys_proto.h> |
| 25 | #include <asm/arch/mem.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 26 | #include <asm/global_data.h> |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 27 | #include <asm/io.h> |
| 28 | #include <asm/emif.h> |
| 29 | #include <asm/gpio.h> |
| 30 | #include <i2c.h> |
| 31 | #include <miiphy.h> |
| 32 | #include <cpsw.h> |
| 33 | #include <power/tps65217.h> |
| 34 | #include <power/tps65910.h> |
Simon Glass | 9d1f619 | 2019-08-02 09:44:25 -0600 | [diff] [blame] | 35 | #include <env_internal.h> |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 36 | #include <watchdog.h> |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 37 | #include "board.h" |
| 38 | |
| 39 | DECLARE_GLOBAL_DATA_PTR; |
| 40 | |
| 41 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
| 42 | |
| 43 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 44 | |
| 45 | static const struct ddr_data ddr3_sl50_data = { |
| 46 | .datardsratio0 = MT41K256M16HA125E_RD_DQS, |
| 47 | .datawdsratio0 = MT41K256M16HA125E_WR_DQS, |
| 48 | .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, |
| 49 | .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, |
| 50 | }; |
| 51 | |
| 52 | static const struct cmd_control ddr3_sl50_cmd_ctrl_data = { |
| 53 | .cmd0csratio = MT41K256M16HA125E_RATIO, |
| 54 | .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| 55 | |
| 56 | .cmd1csratio = MT41K256M16HA125E_RATIO, |
| 57 | .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| 58 | |
| 59 | .cmd2csratio = MT41K256M16HA125E_RATIO, |
| 60 | .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
| 61 | }; |
| 62 | |
| 63 | static struct emif_regs ddr3_sl50_emif_reg_data = { |
| 64 | .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, |
| 65 | .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, |
| 66 | .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, |
| 67 | .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, |
| 68 | .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, |
| 69 | .zq_config = MT41K256M16HA125E_ZQ_CFG, |
| 70 | .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, |
| 71 | }; |
| 72 | |
| 73 | #ifdef CONFIG_SPL_OS_BOOT |
| 74 | int spl_start_uboot(void) |
| 75 | { |
| 76 | /* break into full u-boot on 'c' */ |
| 77 | if (serial_tstc() && serial_getc() == 'c') |
| 78 | return 1; |
| 79 | |
| 80 | #ifdef CONFIG_SPL_ENV_SUPPORT |
| 81 | env_init(); |
Simon Glass | 1753957 | 2017-08-03 12:22:07 -0600 | [diff] [blame] | 82 | env_load(); |
Simon Glass | 22c34c2 | 2017-08-03 12:22:13 -0600 | [diff] [blame] | 83 | if (env_get_yesno("boot_os") != 1) |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 84 | return 1; |
| 85 | #endif |
| 86 | |
| 87 | return 0; |
| 88 | } |
| 89 | #endif |
| 90 | |
| 91 | #define OSC (V_OSCK/1000000) |
| 92 | const struct dpll_params dpll_ddr_sl50 = { |
| 93 | 400, OSC-1, 1, -1, -1, -1, -1}; |
| 94 | |
| 95 | void am33xx_spl_board_init(void) |
| 96 | { |
| 97 | int mpu_vdd; |
| 98 | |
| 99 | /* Get the frequency */ |
| 100 | dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); |
| 101 | |
| 102 | /* BeagleBone PMIC Code */ |
| 103 | int usb_cur_lim; |
| 104 | |
| 105 | if (i2c_probe(TPS65217_CHIP_PM)) |
| 106 | return; |
| 107 | |
| 108 | /* |
| 109 | * Increase USB current limit to 1300mA or 1800mA and set |
| 110 | * the MPU voltage controller as needed. |
| 111 | */ |
| 112 | if (dpll_mpu_opp100.m == MPUPLL_M_1000) { |
| 113 | usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; |
| 114 | mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; |
| 115 | } else { |
| 116 | usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; |
| 117 | mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; |
| 118 | } |
| 119 | |
| 120 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, |
| 121 | TPS65217_POWER_PATH, |
| 122 | usb_cur_lim, |
| 123 | TPS65217_USB_INPUT_CUR_LIMIT_MASK)) |
| 124 | puts("tps65217_reg_write failure\n"); |
| 125 | |
| 126 | /* Set DCDC3 (CORE) voltage to 1.125V */ |
| 127 | if (tps65217_voltage_update(TPS65217_DEFDCDC3, |
| 128 | TPS65217_DCDC_VOLT_SEL_1125MV)) { |
| 129 | puts("tps65217_voltage_update failure\n"); |
| 130 | return; |
| 131 | } |
| 132 | |
| 133 | /* Set CORE Frequencies to OPP100 */ |
| 134 | do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); |
| 135 | |
| 136 | /* Set DCDC2 (MPU) voltage */ |
| 137 | if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { |
| 138 | puts("tps65217_voltage_update failure\n"); |
| 139 | return; |
| 140 | } |
| 141 | |
| 142 | /* |
| 143 | * Set LDO3 to 1.8V and LDO4 to 3.3V |
| 144 | */ |
| 145 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, |
| 146 | TPS65217_DEFLS1, |
| 147 | TPS65217_LDO_VOLTAGE_OUT_1_8, |
| 148 | TPS65217_LDO_MASK)) |
| 149 | puts("tps65217_reg_write failure\n"); |
| 150 | |
| 151 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, |
| 152 | TPS65217_DEFLS2, |
| 153 | TPS65217_LDO_VOLTAGE_OUT_3_3, |
| 154 | TPS65217_LDO_MASK)) |
| 155 | puts("tps65217_reg_write failure\n"); |
| 156 | |
| 157 | /* Set MPU Frequency to what we detected now that voltages are set */ |
| 158 | do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); |
| 159 | } |
| 160 | |
| 161 | const struct dpll_params *get_dpll_ddr_params(void) |
| 162 | { |
| 163 | enable_i2c0_pin_mux(); |
| 164 | i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); |
| 165 | |
| 166 | return &dpll_ddr_sl50; |
| 167 | } |
| 168 | |
| 169 | void set_uart_mux_conf(void) |
| 170 | { |
| 171 | #if CONFIG_CONS_INDEX == 1 |
| 172 | enable_uart0_pin_mux(); |
| 173 | #elif CONFIG_CONS_INDEX == 2 |
| 174 | enable_uart1_pin_mux(); |
| 175 | #elif CONFIG_CONS_INDEX == 3 |
| 176 | enable_uart2_pin_mux(); |
| 177 | #elif CONFIG_CONS_INDEX == 4 |
| 178 | enable_uart3_pin_mux(); |
| 179 | #elif CONFIG_CONS_INDEX == 5 |
| 180 | enable_uart4_pin_mux(); |
| 181 | #elif CONFIG_CONS_INDEX == 6 |
| 182 | enable_uart5_pin_mux(); |
| 183 | #endif |
| 184 | } |
| 185 | |
| 186 | void set_mux_conf_regs(void) |
| 187 | { |
| 188 | enable_board_pin_mux(); |
| 189 | } |
| 190 | |
| 191 | const struct ctrl_ioregs ioregs_evmsk = { |
| 192 | .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, |
| 193 | .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, |
| 194 | .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, |
| 195 | .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, |
| 196 | .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, |
| 197 | }; |
| 198 | |
| 199 | const struct ctrl_ioregs ioregs_bonelt = { |
| 200 | .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 201 | .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 202 | .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 203 | .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 204 | .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, |
| 205 | }; |
| 206 | |
| 207 | const struct ctrl_ioregs ioregs_evm15 = { |
| 208 | .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, |
| 209 | .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, |
| 210 | .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, |
| 211 | .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, |
| 212 | .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, |
| 213 | }; |
| 214 | |
| 215 | const struct ctrl_ioregs ioregs = { |
| 216 | .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 217 | .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 218 | .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 219 | .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 220 | .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
| 221 | }; |
| 222 | |
| 223 | void sdram_init(void) |
| 224 | { |
| 225 | config_ddr(400, &ioregs_bonelt, |
| 226 | &ddr3_sl50_data, |
| 227 | &ddr3_sl50_cmd_ctrl_data, |
| 228 | &ddr3_sl50_emif_reg_data, 0); |
| 229 | } |
| 230 | #endif |
| 231 | |
| 232 | /* |
| 233 | * Basic board specific setup. Pinmux has been handled already. |
| 234 | */ |
| 235 | int board_init(void) |
| 236 | { |
| 237 | #if defined(CONFIG_HW_WATCHDOG) |
| 238 | hw_watchdog_init(); |
| 239 | #endif |
| 240 | |
| 241 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
| 242 | return 0; |
| 243 | } |
| 244 | |
| 245 | #ifdef CONFIG_BOARD_LATE_INIT |
| 246 | int board_late_init(void) |
| 247 | { |
| 248 | return 0; |
| 249 | } |
| 250 | #endif |
| 251 | |
| 252 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
Simon Glass | e5cd9a4 | 2021-07-10 21:14:26 -0600 | [diff] [blame^] | 253 | (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 254 | static void cpsw_control(int enabled) |
| 255 | { |
| 256 | /* VTP can be added here */ |
| 257 | |
| 258 | return; |
| 259 | } |
| 260 | |
| 261 | static struct cpsw_slave_data cpsw_slaves[] = { |
| 262 | { |
| 263 | .slave_reg_ofs = 0x208, |
| 264 | .sliver_reg_ofs = 0xd80, |
| 265 | .phy_addr = 0, |
| 266 | }, |
| 267 | { |
| 268 | .slave_reg_ofs = 0x308, |
| 269 | .sliver_reg_ofs = 0xdc0, |
| 270 | .phy_addr = 1, |
| 271 | }, |
| 272 | }; |
| 273 | |
| 274 | static struct cpsw_platform_data cpsw_data = { |
| 275 | .mdio_base = CPSW_MDIO_BASE, |
| 276 | .cpsw_base = CPSW_BASE, |
| 277 | .mdio_div = 0xff, |
| 278 | .channels = 8, |
| 279 | .cpdma_reg_ofs = 0x800, |
| 280 | .slaves = 1, |
| 281 | .slave_data = cpsw_slaves, |
| 282 | .ale_reg_ofs = 0xd00, |
| 283 | .ale_entries = 1024, |
| 284 | .host_port_reg_ofs = 0x108, |
| 285 | .hw_stats_reg_ofs = 0x900, |
| 286 | .bd_ram_ofs = 0x2000, |
| 287 | .mac_control = (1 << 5), |
| 288 | .control = cpsw_control, |
| 289 | .host_port_num = 0, |
| 290 | .version = CPSW_CTRL_VERSION_2, |
| 291 | }; |
| 292 | #endif |
| 293 | |
| 294 | /* |
| 295 | * This function will: |
| 296 | * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr |
| 297 | * in the environment |
| 298 | * Perform fixups to the PHY present on certain boards. We only need this |
| 299 | * function in: |
| 300 | * - SPL with either CPSW or USB ethernet support |
| 301 | * - Full U-Boot, with either CPSW or USB ethernet |
| 302 | * Build in only these cases to avoid warnings about unused variables |
| 303 | * when we build an SPL that has neither option but full U-Boot will. |
| 304 | */ |
Simon Glass | e5cd9a4 | 2021-07-10 21:14:26 -0600 | [diff] [blame^] | 305 | #if ((defined(CONFIG_SPL_ETH) || defined(CONFIG_SPL_USB_ETHER)) \ |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 306 | && defined(CONFIG_SPL_BUILD)) || \ |
| 307 | ((defined(CONFIG_DRIVER_TI_CPSW) || \ |
| 308 | defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ |
| 309 | !defined(CONFIG_SPL_BUILD)) |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 310 | int board_eth_init(struct bd_info *bis) |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 311 | { |
| 312 | int rv, n = 0; |
| 313 | uint8_t mac_addr[6]; |
| 314 | uint32_t mac_hi, mac_lo; |
| 315 | |
| 316 | /* try reading mac address from efuse */ |
| 317 | mac_lo = readl(&cdev->macid0l); |
| 318 | mac_hi = readl(&cdev->macid0h); |
| 319 | mac_addr[0] = mac_hi & 0xFF; |
| 320 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 321 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 322 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 323 | mac_addr[4] = mac_lo & 0xFF; |
| 324 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
| 325 | |
| 326 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
Simon Glass | e5cd9a4 | 2021-07-10 21:14:26 -0600 | [diff] [blame^] | 327 | (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)) |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 328 | if (!env_get("ethaddr")) { |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 329 | printf("<ethaddr> not set. Validating first E-fuse MAC\n"); |
| 330 | |
| 331 | if (is_valid_ethaddr(mac_addr)) |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 332 | eth_env_set_enetaddr("ethaddr", mac_addr); |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 333 | } |
| 334 | |
| 335 | #ifdef CONFIG_DRIVER_TI_CPSW |
| 336 | |
| 337 | mac_lo = readl(&cdev->macid1l); |
| 338 | mac_hi = readl(&cdev->macid1h); |
| 339 | mac_addr[0] = mac_hi & 0xFF; |
| 340 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 341 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 342 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 343 | mac_addr[4] = mac_lo & 0xFF; |
| 344 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
| 345 | |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 346 | if (!env_get("eth1addr")) { |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 347 | if (is_valid_ethaddr(mac_addr)) |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 348 | eth_env_set_enetaddr("eth1addr", mac_addr); |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 349 | } |
| 350 | |
| 351 | |
| 352 | writel(MII_MODE_ENABLE, &cdev->miisel); |
| 353 | cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = |
| 354 | PHY_INTERFACE_MODE_MII; |
| 355 | |
| 356 | rv = cpsw_register(&cpsw_data); |
| 357 | if (rv < 0) |
| 358 | printf("Error %d registering CPSW switch\n", rv); |
| 359 | else |
| 360 | n += rv; |
| 361 | #endif |
| 362 | |
| 363 | /* |
| 364 | * |
| 365 | * CPSW RGMII Internal Delay Mode is not supported in all PVT |
| 366 | * operating points. So we must set the TX clock delay feature |
| 367 | * in the AR8051 PHY. Since we only support a single ethernet |
| 368 | * device in U-Boot, we only do this for the first instance. |
| 369 | */ |
| 370 | #define AR8051_PHY_DEBUG_ADDR_REG 0x1d |
| 371 | #define AR8051_PHY_DEBUG_DATA_REG 0x1e |
| 372 | #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 |
| 373 | #define AR8051_RGMII_TX_CLK_DLY 0x100 |
| 374 | |
| 375 | #endif |
| 376 | #if defined(CONFIG_USB_ETHER) && \ |
Faiz Abbas | c01553b | 2018-02-16 21:17:44 +0530 | [diff] [blame] | 377 | (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 378 | if (is_valid_ether_addr(mac_addr)) |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 379 | eth_env_set_enetaddr("usbnet_devaddr", mac_addr); |
Enric Balletbò i Serra | 9d89b08 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 380 | |
| 381 | rv = usb_eth_initialize(bis); |
| 382 | if (rv < 0) |
| 383 | printf("Error %d registering USB_ETHER\n", rv); |
| 384 | else |
| 385 | n += rv; |
| 386 | #endif |
| 387 | return n; |
| 388 | } |
| 389 | #endif |