Fabio Estevam | db1aa29 | 2021-05-28 10:26:57 -0300 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2016 NXP Semiconductors |
| 4 | * Copyright (C) 2021 Fabio Estevam <festevam@denx.de> |
| 5 | * |
| 6 | * Configuration settings for the smegw01 board. |
| 7 | */ |
| 8 | |
| 9 | #ifndef __SMEGW01_CONFIG_H |
| 10 | #define __SMEGW01_CONFIG_H |
| 11 | |
| 12 | #include "mx7_common.h" |
| 13 | #include <imximage.h> |
| 14 | |
| 15 | #define PHYS_SDRAM_SIZE SZ_512M |
| 16 | |
Fabio Estevam | db1aa29 | 2021-05-28 10:26:57 -0300 | [diff] [blame] | 17 | /* MMC Config*/ |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 18 | #define CFG_SYS_FSL_ESDHC_ADDR 0 |
Fabio Estevam | db1aa29 | 2021-05-28 10:26:57 -0300 | [diff] [blame] | 19 | |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 20 | #define CFG_EXTRA_ENV_SETTINGS \ |
Fabio Estevam | db1aa29 | 2021-05-28 10:26:57 -0300 | [diff] [blame] | 21 | "image=zImage\0" \ |
| 22 | "console=ttymxc0\0" \ |
| 23 | "fdtfile=imx7d-smegw01.dtb\0" \ |
| 24 | "fdt_addr=0x83000000\0" \ |
| 25 | "bootm_size=0x10000000\0" \ |
| 26 | "mmcdev=0\0" \ |
| 27 | "mmcpart=1\0" \ |
Fabio Estevam | db1aa29 | 2021-05-28 10:26:57 -0300 | [diff] [blame] | 28 | "mmcargs=setenv bootargs console=${console},${baudrate} " \ |
Fabio Estevam | 3a1291c | 2021-08-24 07:58:46 -0300 | [diff] [blame] | 29 | "root=/dev/mmcblk0p${mmcpart} rootwait rw\0" \ |
Fabio Estevam | 8fd783d | 2021-06-15 20:38:38 -0300 | [diff] [blame] | 30 | "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \ |
| 31 | "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \ |
Fabio Estevam | db1aa29 | 2021-05-28 10:26:57 -0300 | [diff] [blame] | 32 | "mmcboot=echo Booting from mmc ...; " \ |
| 33 | "run mmcargs; " \ |
| 34 | "if run loadfdt; then " \ |
| 35 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
| 36 | "fi;\0" \ |
| 37 | |
Fabio Estevam | db1aa29 | 2021-05-28 10:26:57 -0300 | [diff] [blame] | 38 | /* Physical Memory Map */ |
| 39 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
| 40 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 41 | #define CFG_SYS_SDRAM_BASE PHYS_SDRAM |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 42 | #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
| 43 | #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE |
Fabio Estevam | db1aa29 | 2021-05-28 10:26:57 -0300 | [diff] [blame] | 44 | |
Fabio Estevam | db1aa29 | 2021-05-28 10:26:57 -0300 | [diff] [blame] | 45 | #endif |