| Mike Frysinger | 66c4cf4 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 1 | /* |
| 2 | * General Purpose Timer Masks |
| 3 | */ |
| 4 | |
| 5 | #ifndef __BFIN_PERIPHERAL_TIMER__ |
| 6 | #define __BFIN_PERIPHERAL_TIMER__ |
| 7 | |
| 8 | /* TIMER_ENABLE Masks */ |
| 9 | #define TIMEN0 0x0001 /* Enable Timer 0 */ |
| 10 | #define TIMEN1 0x0002 /* Enable Timer 1 */ |
| 11 | #define TIMEN2 0x0004 /* Enable Timer 2 */ |
| 12 | #define TIMEN3 0x0008 /* Enable Timer 3 */ |
| 13 | #define TIMEN4 0x0010 /* Enable Timer 4 */ |
| 14 | #define TIMEN5 0x0020 /* Enable Timer 5 */ |
| 15 | #define TIMEN6 0x0040 /* Enable Timer 6 */ |
| 16 | #define TIMEN7 0x0080 /* Enable Timer 7 */ |
| 17 | |
| 18 | /* TIMER_DISABLE Masks */ |
| 19 | #define TIMDIS0 TIMEN0 /* Disable Timer 0 */ |
| 20 | #define TIMDIS1 TIMEN1 /* Disable Timer 1 */ |
| 21 | #define TIMDIS2 TIMEN2 /* Disable Timer 2 */ |
| 22 | #define TIMDIS3 TIMEN3 /* Disable Timer 3 */ |
| 23 | #define TIMDIS4 TIMEN4 /* Disable Timer 4 */ |
| 24 | #define TIMDIS5 TIMEN5 /* Disable Timer 5 */ |
| 25 | #define TIMDIS6 TIMEN6 /* Disable Timer 6 */ |
| 26 | #define TIMDIS7 TIMEN7 /* Disable Timer 7 */ |
| 27 | |
| 28 | /* TIMER_STATUS Masks */ |
| 29 | #define TIMIL0 0x00000001 /* Timer 0 Interrupt */ |
| 30 | #define TIMIL1 0x00000002 /* Timer 1 Interrupt */ |
| 31 | #define TIMIL2 0x00000004 /* Timer 2 Interrupt */ |
| 32 | #define TIMIL3 0x00000008 /* Timer 3 Interrupt */ |
| 33 | #define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ |
| 34 | #define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ |
| 35 | #define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ |
| 36 | #define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ |
| 37 | #define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ |
| 38 | #define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ |
| 39 | #define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ |
| 40 | #define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ |
| 41 | #define TIMIL4 0x00010000 /* Timer 4 Interrupt */ |
| 42 | #define TIMIL5 0x00020000 /* Timer 5 Interrupt */ |
| 43 | #define TIMIL6 0x00040000 /* Timer 6 Interrupt */ |
| 44 | #define TIMIL7 0x00080000 /* Timer 7 Interrupt */ |
| 45 | #define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ |
| 46 | #define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ |
| 47 | #define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ |
| 48 | #define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ |
| 49 | #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ |
| 50 | #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ |
| 51 | #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ |
| 52 | #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ |
| 53 | |
| 54 | /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ |
| 55 | #define TOVL_ERR0 TOVF_ERR0 |
| 56 | #define TOVL_ERR1 TOVF_ERR1 |
| 57 | #define TOVL_ERR2 TOVF_ERR2 |
| 58 | #define TOVL_ERR3 TOVF_ERR3 |
| 59 | #define TOVL_ERR4 TOVF_ERR4 |
| 60 | #define TOVL_ERR5 TOVF_ERR5 |
| 61 | #define TOVL_ERR6 TOVF_ERR6 |
| 62 | #define TOVL_ERR7 TOVF_ERR7 |
| 63 | |
| 64 | /* TIMERx_CONFIG Masks */ |
| 65 | #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ |
| 66 | #define WDTH_CAP 0x0002 /* Width Capture Input Mode */ |
| 67 | #define EXT_CLK 0x0003 /* External Clock Mode */ |
| 68 | #define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ |
| 69 | #define PERIOD_CNT 0x0008 /* Period Count */ |
| 70 | #define IRQ_ENA 0x0010 /* Interrupt Request Enable */ |
| 71 | #define TIN_SEL 0x0020 /* Timer Input Select */ |
| 72 | #define OUT_DIS 0x0040 /* Output Pad Disable */ |
| 73 | #define CLK_SEL 0x0080 /* Timer Clock Select */ |
| 74 | #define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ |
| 75 | #define EMU_RUN 0x0200 /* Emulation Behavior Select */ |
| 76 | #define ERR_TYP 0xC000 /* Error Type */ |
| 77 | |
| 78 | #endif |