| Mike Frysinger | 66c4cf4 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Enhanced PPI (EPPI) |
| 3 | */ |
| 4 | |
| 5 | #ifndef __BFIN_PERIPHERAL_EPPI__ |
| 6 | #define __BFIN_PERIPHERAL_EPPI__ |
| 7 | |
| 8 | /* Bit masks for EPPIx_STATUS */ |
| 9 | #define CFIFO_ERR 0x0001 /* Chroma FIFO Error */ |
| 10 | #define YFIFO_ERR 0x0002 /* Luma FIFO Error */ |
| 11 | #define LTERR_OVR 0x0004 /* Line Track Overflow */ |
| 12 | #define LTERR_UNDR 0x0008 /* Line Track Underflow */ |
| 13 | #define FTERR_OVR 0x0010 /* Frame Track Overflow */ |
| 14 | #define FTERR_UNDR 0x0020 /* Frame Track Underflow */ |
| 15 | #define ERR_NCOR 0x0040 /* Preamble Error Not Corrected */ |
| 16 | #define DMA1URQ 0x0080 /* DMA1 Urgent Request */ |
| 17 | #define DMA0URQ 0x0100 /* DMA0 Urgent Request */ |
| 18 | #define ERR_DET 0x4000 /* Preamble Error Detected */ |
| 19 | #define FLD 0x8000 /* Field */ |
| 20 | |
| 21 | /* Bit masks for EPPIx_CONTROL */ |
| 22 | #define EPPI_EN 0x00000001 /* Enable */ |
| 23 | #define EPPI_DIR 0x00000002 /* Direction */ |
| 24 | #define XFR_TYPE 0x0000000c /* Operating Mode */ |
| 25 | #define FS_CFG 0x00000030 /* Frame Sync Configuration */ |
| 26 | #define FLD_SEL 0x00000040 /* Field Select/Trigger */ |
| 27 | #define ITU_TYPE 0x00000080 /* ITU Interlaced or Progressive */ |
| 28 | #define BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */ |
| 29 | #define ICLKGEN 0x00000200 /* Internal Clock Generation */ |
| 30 | #define IFSGEN 0x00000400 /* Internal Frame Sync Generation */ |
| 31 | #define POLC 0x00001800 /* Frame Sync and Data Driving/Sampling Edges */ |
| 32 | #define POLS 0x00006000 /* Frame Sync Polarity */ |
| 33 | #define DLENGTH 0x00038000 /* Data Length */ |
| 34 | #define SKIP_EN 0x00040000 /* Skip Enable */ |
| 35 | #define SKIP_EO 0x00080000 /* Skip Even or Odd */ |
| 36 | #define PACKEN 0x00100000 /* Packing/Unpacking Enable */ |
| 37 | #define SWAPEN 0x00200000 /* Swap Enable */ |
| 38 | #define SIGN_EXT 0x00400000 /* Sign Extension or Zero-filled / Data Split Format */ |
| 39 | #define SPLT_EVEN_ODD 0x00800000 /* Split Even and Odd Data Samples */ |
| 40 | #define SUBSPLT_ODD 0x01000000 /* Sub-split Odd Samples */ |
| 41 | #define DMACFG 0x02000000 /* One or Two DMA Channels Mode */ |
| 42 | #define RGB_FMT_EN 0x04000000 /* RGB Formatting Enable */ |
| 43 | #define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ |
| 44 | #define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ |
| 45 | |
| 46 | #define DLEN_8 (0 << 15) /* 000 - 8 bits */ |
| 47 | #define DLEN_10 (1 << 15) /* 001 - 10 bits */ |
| 48 | #define DLEN_12 (2 << 15) /* 010 - 12 bits */ |
| 49 | #define DLEN_14 (3 << 15) /* 011 - 14 bits */ |
| 50 | #define DLEN_16 (4 << 15) /* 100 - 16 bits */ |
| 51 | #define DLEN_18 (5 << 15) /* 101 - 18 bits */ |
| 52 | #define DLEN_24 (6 << 15) /* 110 - 24 bits */ |
| 53 | |
| 54 | /* Bit masks for EPPIx_FS2W_LVB */ |
| 55 | #define F1VB_BD 0x000000ff /* Vertical Blanking before Field 1 Active Data */ |
| 56 | #define F1VB_AD 0x0000ff00 /* Vertical Blanking after Field 1 Active Data */ |
| 57 | #define F2VB_BD 0x00ff0000 /* Vertical Blanking before Field 2 Active Data */ |
| 58 | #define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */ |
| 59 | |
| 60 | /* Bit masks for EPPIx_FS2W_LAVF */ |
| 61 | #define F1_ACT 0x0000ffff /* Number of Lines of Active Data in Field 1 */ |
| 62 | #define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */ |
| 63 | |
| 64 | /* Bit masks for EPPIx_CLIP */ |
| 65 | #define LOW_ODD 0x000000ff /* Lower Limit for Odd Bytes (Chroma) */ |
| 66 | #define HIGH_ODD 0x0000ff00 /* Upper Limit for Odd Bytes (Chroma) */ |
| 67 | #define LOW_EVEN 0x00ff0000 /* Lower Limit for Even Bytes (Luma) */ |
| 68 | #define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ |
| 69 | |
| 70 | #endif |