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git01.mediatek.com / filogic / uboot / e55aadd77d7602e8d25321d4d4257092de72984d / . / arch / arm / cpu / u-boot.lds
blob: 3037885b1270ddaa5f502bfe24fdbe3b2fe829bc [file] [log] [blame]
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]1/*
2 * Copyright (c) 2004-2008 Texas Instruments
3 *
4 * (C) Copyright 2002
5 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
27OUTPUT_ARCH(arm)
28ENTRY(_start)
29SECTIONS
30{
31 . = 0x00000000;
32
33 . = ALIGN(4);
34 .text :
35 {
Albert ARIBAUDc53687e2013-06-11 14:17:33 +0200[diff] [blame]36 *(.__image_copy_start)
Stephen Warrenadddf452012-10-22 06:19:32 +0000[diff] [blame]37 CPUDIR/start.o (.text*)
38 *(.text*)
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]39 }
40
41 . = ALIGN(4);
42 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
43
44 . = ALIGN(4);
45 .data : {
Stephen Warrenadddf452012-10-22 06:19:32 +0000[diff] [blame]46 *(.data*)
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]47 }
48
49 . = ALIGN(4);
50
51 . = .;
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]52
53 . = ALIGN(4);
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]54 .u_boot_list : {
Albert ARIBAUDc24895e2013-02-25 00:59:00 +0000[diff] [blame]55 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]56 }
57
58 . = ALIGN(4);
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]59
Albert ARIBAUDc53687e2013-06-11 14:17:33 +0200[diff] [blame]60 .image_copy_end :
61 {
62 *(.__image_copy_end)
63 }
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]64
Albert ARIBAUDaf3ff162013-06-11 14:17:34 +0200[diff] [blame]65 .rel_dyn_start :
66 {
67 *(.__rel_dyn_start)
68 }
69
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]70 .rel.dyn : {
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]71 *(.rel*)
Albert ARIBAUDaf3ff162013-06-11 14:17:34 +0200[diff] [blame]72 }
73
74 .rel_dyn_end :
75 {
76 *(.__rel_dyn_end)
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]77 }
78
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]79 _end = .;
80
81 /*
82 * Deprecated: this MMU section is used by pxa at present but
83 * should not be used by new boards/CPUs.
84 */
85 . = ALIGN(4096);
86 .mmutable : {
87 *(.mmutable)
88 }
89
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]90/*
91 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
92 * __bss_base and __bss_limit are for linker only (overlay ordering)
93 */
94
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]95 .bss_start __rel_dyn_start (OVERLAY) : {
96 KEEP(*(.__bss_start));
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]97 __bss_base = .;
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]98 }
99
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]100 .bss __bss_base (OVERLAY) : {
Stephen Warrenadddf452012-10-22 06:19:32 +0000[diff] [blame]101 *(.bss*)
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]102 . = ALIGN(4);
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]103 __bss_limit = .;
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]104 }
Tom Rini19aac972013-03-18 12:31:00 -0400[diff] [blame]105
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]106 .bss_end __bss_limit (OVERLAY) : {
107 KEEP(*(.__bss_end));
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]108 }
109
Albert ARIBAUD16915932013-06-11 14:17:31 +0200[diff] [blame]110 /DISCARD/ : { *(.dynsym) }
Simon Glass437e2b82012-02-23 03:28:41 +0000[diff] [blame]111 /DISCARD/ : { *(.dynstr*) }
112 /DISCARD/ : { *(.dynamic*) }
113 /DISCARD/ : { *(.plt*) }
114 /DISCARD/ : { *(.interp*) }
115 /DISCARD/ : { *(.gnu*) }
116}