Alex Marginean | 0649be5 | 2019-07-12 10:13:53 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2019 |
| 4 | * Alex Marginean, NXP |
| 5 | */ |
| 6 | |
Tom Rini | abb9a04 | 2024-05-18 20:20:43 -0600 | [diff] [blame] | 7 | #include <common.h> |
Alex Marginean | 0649be5 | 2019-07-12 10:13:53 +0300 | [diff] [blame] | 8 | #include <dm.h> |
Simon Glass | 75c4d41 | 2020-07-19 10:15:37 -0600 | [diff] [blame] | 9 | #include <miiphy.h> |
Alex Marginean | 0649be5 | 2019-07-12 10:13:53 +0300 | [diff] [blame] | 10 | #include <misc.h> |
Simon Glass | 75c4d41 | 2020-07-19 10:15:37 -0600 | [diff] [blame] | 11 | #include <dm/test.h> |
| 12 | #include <test/test.h> |
Alex Marginean | 0649be5 | 2019-07-12 10:13:53 +0300 | [diff] [blame] | 13 | #include <test/ut.h> |
Alex Marginean | 0649be5 | 2019-07-12 10:13:53 +0300 | [diff] [blame] | 14 | |
| 15 | /* macros copied over from mdio_sandbox.c */ |
| 16 | #define SANDBOX_PHY_ADDR 5 |
| 17 | #define SANDBOX_PHY_REG_CNT 2 |
| 18 | |
| 19 | #define TEST_REG_VALUE 0xabcd |
| 20 | |
| 21 | static int dm_test_mdio_mux(struct unit_test_state *uts) |
| 22 | { |
| 23 | struct uclass *uc; |
| 24 | struct udevice *mux; |
| 25 | struct udevice *mdio_ch0, *mdio_ch1, *mdio; |
| 26 | struct mdio_ops *ops, *ops_parent; |
| 27 | struct mdio_mux_ops *mmops; |
| 28 | u16 reg; |
| 29 | |
| 30 | ut_assertok(uclass_get(UCLASS_MDIO_MUX, &uc)); |
| 31 | |
| 32 | ut_assertok(uclass_get_device_by_name(UCLASS_MDIO_MUX, "mdio-mux-test", |
| 33 | &mux)); |
| 34 | |
| 35 | ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-ch-test@0", |
| 36 | &mdio_ch0)); |
| 37 | ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-ch-test@1", |
| 38 | &mdio_ch1)); |
| 39 | |
| 40 | ut_assertok(uclass_get_device_by_name(UCLASS_MDIO, "mdio-test", &mdio)); |
| 41 | |
| 42 | ops = mdio_get_ops(mdio_ch0); |
| 43 | ut_assertnonnull(ops); |
| 44 | ut_assertnonnull(ops->read); |
| 45 | ut_assertnonnull(ops->write); |
| 46 | |
| 47 | mmops = mdio_mux_get_ops(mux); |
| 48 | ut_assertnonnull(mmops); |
| 49 | ut_assertnonnull(mmops->select); |
| 50 | |
| 51 | ops_parent = mdio_get_ops(mdio); |
| 52 | ut_assertnonnull(ops); |
| 53 | ut_assertnonnull(ops->read); |
| 54 | |
| 55 | /* |
| 56 | * mux driver sets last register on the emulated PHY whenever a group |
| 57 | * is selected to the selection #. Just reading that register from |
| 58 | * either of the child buses should return the id of the child bus |
| 59 | */ |
Marek Behún | e4dedf2 | 2022-04-07 00:32:59 +0200 | [diff] [blame] | 60 | reg = dm_mdio_read(mdio_ch0, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE, |
| 61 | SANDBOX_PHY_REG_CNT - 1); |
Alex Marginean | 0649be5 | 2019-07-12 10:13:53 +0300 | [diff] [blame] | 62 | ut_asserteq(reg, 0); |
| 63 | |
Marek Behún | e4dedf2 | 2022-04-07 00:32:59 +0200 | [diff] [blame] | 64 | reg = dm_mdio_read(mdio_ch1, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE, |
| 65 | SANDBOX_PHY_REG_CNT - 1); |
Alex Marginean | 0649be5 | 2019-07-12 10:13:53 +0300 | [diff] [blame] | 66 | ut_asserteq(reg, 1); |
| 67 | |
| 68 | mmops->select(mux, MDIO_MUX_SELECT_NONE, 5); |
Marek Behún | e4dedf2 | 2022-04-07 00:32:59 +0200 | [diff] [blame] | 69 | reg = dm_mdio_read(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE, |
| 70 | SANDBOX_PHY_REG_CNT - 1); |
Alex Marginean | 0649be5 | 2019-07-12 10:13:53 +0300 | [diff] [blame] | 71 | ut_asserteq(reg, 5); |
| 72 | |
| 73 | mmops->deselect(mux, 5); |
Marek Behún | e4dedf2 | 2022-04-07 00:32:59 +0200 | [diff] [blame] | 74 | reg = dm_mdio_read(mdio, SANDBOX_PHY_ADDR, MDIO_DEVAD_NONE, |
| 75 | SANDBOX_PHY_REG_CNT - 1); |
Alex Marginean | 0649be5 | 2019-07-12 10:13:53 +0300 | [diff] [blame] | 76 | ut_asserteq(reg, (u16)MDIO_MUX_SELECT_NONE); |
| 77 | |
| 78 | return 0; |
| 79 | } |
| 80 | |
Simon Glass | 974dccd | 2020-07-28 19:41:12 -0600 | [diff] [blame] | 81 | DM_TEST(dm_test_mdio_mux, UT_TESTF_SCAN_FDT); |