blob: ef3649688c66f9977f1ac3f22bc28a64ef3f526d [file] [log] [blame]
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +01001// SPDX-License-Identifier: GPL-2.0+
2
Tom Riniabb9a042024-05-18 20:20:43 -06003#include <common.h>
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +01004#include <asm/io.h>
5#include <memalign.h>
6#include <nand.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -06007#include <linux/bitops.h>
Simon Glassd66c5f72020-02-03 07:36:15 -07008#include <linux/err.h>
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +01009#include <linux/errno.h>
10#include <linux/io.h>
11#include <linux/ioport.h>
12#include <dm.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060013#include <linux/printk.h>
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +010014
15#include "brcmnand.h"
16
17struct bcm6838_nand_soc {
18 struct brcmnand_soc soc;
19 void __iomem *base;
20};
21
22#define BCM6838_NAND_INT 0x00
23#define BCM6838_NAND_STATUS_SHIFT 0
24#define BCM6838_NAND_STATUS_MASK (0xfff << BCM6838_NAND_STATUS_SHIFT)
25#define BCM6838_NAND_ENABLE_SHIFT 16
26#define BCM6838_NAND_ENABLE_MASK (0xffff << BCM6838_NAND_ENABLE_SHIFT)
27
28enum {
29 BCM6838_NP_READ = BIT(0),
30 BCM6838_BLOCK_ERASE = BIT(1),
31 BCM6838_COPY_BACK = BIT(2),
32 BCM6838_PAGE_PGM = BIT(3),
33 BCM6838_CTRL_READY = BIT(4),
34 BCM6838_DEV_RBPIN = BIT(5),
35 BCM6838_ECC_ERR_UNC = BIT(6),
36 BCM6838_ECC_ERR_CORR = BIT(7),
37};
38
39static bool bcm6838_nand_intc_ack(struct brcmnand_soc *soc)
40{
41 struct bcm6838_nand_soc *priv =
42 container_of(soc, struct bcm6838_nand_soc, soc);
43 void __iomem *mmio = priv->base + BCM6838_NAND_INT;
44 u32 val = brcmnand_readl(mmio);
45
46 if (val & (BCM6838_CTRL_READY << BCM6838_NAND_STATUS_SHIFT)) {
47 /* Ack interrupt */
48 val &= ~BCM6838_NAND_STATUS_MASK;
49 val |= BCM6838_CTRL_READY << BCM6838_NAND_STATUS_SHIFT;
50 brcmnand_writel(val, mmio);
51 return true;
52 }
53
54 return false;
55}
56
57static void bcm6838_nand_intc_set(struct brcmnand_soc *soc, bool en)
58{
59 struct bcm6838_nand_soc *priv =
60 container_of(soc, struct bcm6838_nand_soc, soc);
61 void __iomem *mmio = priv->base + BCM6838_NAND_INT;
62 u32 val = brcmnand_readl(mmio);
63
64 /* Don't ack any interrupts */
65 val &= ~BCM6838_NAND_STATUS_MASK;
66
67 if (en)
68 val |= BCM6838_CTRL_READY << BCM6838_NAND_ENABLE_SHIFT;
69 else
70 val &= ~(BCM6838_CTRL_READY << BCM6838_NAND_ENABLE_SHIFT);
71
72 brcmnand_writel(val, mmio);
73}
74
75static int bcm6838_nand_probe(struct udevice *dev)
76{
77 struct udevice *pdev = dev;
78 struct bcm6838_nand_soc *priv = dev_get_priv(dev);
79 struct brcmnand_soc *soc;
80 struct resource res;
81
82 soc = &priv->soc;
83
84 dev_read_resource_byname(pdev, "nand-int-base", &res);
85 priv->base = ioremap(res.start, resource_size(&res));
86 if (IS_ERR(priv->base))
87 return PTR_ERR(priv->base);
88
89 soc->ctlrdy_ack = bcm6838_nand_intc_ack;
90 soc->ctlrdy_set_enabled = bcm6838_nand_intc_set;
91
92 /* Disable and ack all interrupts */
93 brcmnand_writel(0, priv->base + BCM6838_NAND_INT);
94 brcmnand_writel(BCM6838_NAND_STATUS_MASK,
95 priv->base + BCM6838_NAND_INT);
96
97 return brcmnand_probe(pdev, soc);
98}
99
100static const struct udevice_id bcm6838_nand_dt_ids[] = {
101 {
102 .compatible = "brcm,nand-bcm6838",
103 },
104 { /* sentinel */ }
105};
106
107U_BOOT_DRIVER(bcm6838_nand) = {
108 .name = "bcm6838-nand",
109 .id = UCLASS_MTD,
110 .of_match = bcm6838_nand_dt_ids,
111 .probe = bcm6838_nand_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700112 .priv_auto = sizeof(struct bcm6838_nand_soc),
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100113};
114
115void board_nand_init(void)
116{
117 struct udevice *dev;
118 int ret;
119
120 ret = uclass_get_device_by_driver(UCLASS_MTD,
Simon Glass65130cd2020-12-28 20:34:56 -0700121 DM_DRIVER_GET(bcm6838_nand), &dev);
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100122 if (ret && ret != -ENODEV)
123 pr_err("Failed to initialize %s. (error %d)\n", dev->name,
124 ret);
125}