blob: d4ee21dfc07f83580926dbe80b04b4bdd2fd6460 [file] [log] [blame]
Michal Simek113ca2e2022-02-23 15:52:03 +01001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Xilinx Inc.
4 */
5
Tom Riniabb9a042024-05-18 20:20:43 -06006#include <common.h>
Michal Simek113ca2e2022-02-23 15:52:03 +01007#include <cpu_func.h>
8#include <dm.h>
9#include <dma.h>
10#include <dma-uclass.h>
11#include <errno.h>
12#include <dm/device_compat.h>
13
14/**
15 * struct zynqmp_dpdma_priv - Private structure
16 * @dev: Device uclass for video_ops
17 */
18struct zynqmp_dpdma_priv {
19 struct udevice *dev;
20};
21
22static int zynqmp_dpdma_probe(struct udevice *dev)
23{
24 /* Only placeholder for power domain driver */
25 return 0;
26}
27
28static const struct dma_ops zynqmp_dpdma_ops = {
29};
30
31static const struct udevice_id zynqmp_dpdma_ids[] = {
32 { .compatible = "xlnx,zynqmp-dpdma" },
33 { }
34};
35
36U_BOOT_DRIVER(zynqmp_dpdma) = {
37 .name = "zynqmp_dpdma",
38 .id = UCLASS_DMA,
39 .of_match = zynqmp_dpdma_ids,
40 .ops = &zynqmp_dpdma_ops,
41 .probe = zynqmp_dpdma_probe,
42 .priv_auto = sizeof(struct zynqmp_dpdma_priv),
43};