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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -05002/*
Kumar Galae727a362011-01-12 02:48:53 -06003 * Copyright 2007-2009, 2011 Freescale Semiconductor, Inc.
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -05004 */
5
Masahiro Yamadacd1b58e2014-04-28 10:17:10 +09006#include "config.h"
Kumar Galae727a362011-01-12 02:48:53 -06007
Tom Riniaac81492022-12-04 10:13:40 -05008#ifdef CFG_RESET_VECTOR_ADDRESS
9#define RESET_VECTOR_ADDRESS CFG_RESET_VECTOR_ADDRESS
Kumar Galae727a362011-01-12 02:48:53 -060010#else
Kumar Gala6472af82009-09-09 11:40:41 -050011#define RESET_VECTOR_ADDRESS 0xfffffffc
12#endif
13
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050014OUTPUT_ARCH(powerpc)
Pali Rohár3f9f1bd2022-04-03 00:05:09 +020015ENTRY(_start)
Peter Tyser1047c162010-09-29 14:05:56 -050016
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050017SECTIONS
18{
Pali Rohárb9304822022-05-11 20:57:31 +020019 /* Optional boot sector */
20#if defined(CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR) && !defined(CONFIG_SPL)
Simon Glass72cc5382022-10-20 18:22:39 -060021 .bootsect CONFIG_TEXT_BASE - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 : {
Pali Rohárb9304822022-05-11 20:57:31 +020022 KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootsect))
23 . = CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512;
24 }
25#endif
26
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050027 /* Read-only sections, merged into text segment: */
Pali Rohár18209f72022-06-16 14:19:44 +020028 .text :
Pali Rohárd61e3c22022-04-05 15:12:35 +020029 {
Tom Rini667dd4f2022-06-10 22:59:37 -040030#if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
Pali Rohárd61e3c22022-04-05 15:12:35 +020031 KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
Pali Rohárd61e3c22022-04-05 15:12:35 +020032#endif
Peter Tyser1047c162010-09-29 14:05:56 -050033 *(.text*)
Pali Rohár18209f72022-06-16 14:19:44 +020034 }
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050035 _etext = .;
36 PROVIDE (etext = .);
37 .rodata :
38 {
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050039 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
Pali Rohár18209f72022-06-16 14:19:44 +020040 }
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050041
42 /* Read-write section, merged into data segment: */
43 . = (. + 0x00FF) & 0xFFFFFF00;
44 _erotext = .;
45 PROVIDE (erotext = .);
46 .reloc :
47 {
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050048 _GOT2_TABLE_ = .;
Peter Tyser1047c162010-09-29 14:05:56 -050049 KEEP(*(.got2))
Joakim Tjernlund42126a62010-12-03 17:30:37 +010050 KEEP(*(.got))
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050051 _FIXUP_TABLE_ = .;
Peter Tyser1047c162010-09-29 14:05:56 -050052 KEEP(*(.fixup))
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050053 }
Joakim Tjernlund42126a62010-12-03 17:30:37 +010054 __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050055 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
56
57 .data :
58 {
Peter Tyser1047c162010-09-29 14:05:56 -050059 *(.data*)
60 *(.sdata*)
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050061 }
62 _edata = .;
63 PROVIDE (edata = .);
64
65 . = .;
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050066
Marek Vasut607092a2012-10-12 10:27:03 +000067 . = ALIGN(4);
Andrew Scull5a9095c2022-05-30 10:00:04 +000068 __u_boot_list : {
69 KEEP(*(SORT(__u_boot_list*)));
Marek Vasut607092a2012-10-12 10:27:03 +000070 }
71
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050072 . = .;
73 __start___ex_table = .;
74 __ex_table : { *(__ex_table) }
75 __stop___ex_table = .;
76
Pali Rohár0486cb62022-04-05 15:12:30 +020077 . = ALIGN(4);
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050078 __init_begin = .;
79 .text.init : { *(.text.init) }
80 .data.init : { *(.data.init) }
Pali Rohár0486cb62022-04-05 15:12:30 +020081 . = ALIGN(4);
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050082 __init_end = .;
Jagdish Gediya910e1ae2018-09-03 21:35:05 +053083 _end = .;
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050084
Tom Rini667dd4f2022-06-10 22:59:37 -040085#if !CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC)
Kumar Gala6472af82009-09-09 11:40:41 -050086 .bootpg RESET_VECTOR_ADDRESS - 0xffc :
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050087 {
Stefan Roese88fbf932010-04-15 16:07:28 +020088 arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
Pali Rohár18209f72022-06-16 14:19:44 +020089 } = 0xffff
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050090
Kumar Gala6472af82009-09-09 11:40:41 -050091 .resetvec RESET_VECTOR_ADDRESS :
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050092 {
Peter Tyser1047c162010-09-29 14:05:56 -050093 KEEP(*(.resetvec))
Pali Rohár18209f72022-06-16 14:19:44 +020094 } = 0xffff
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050095
Kumar Gala6472af82009-09-09 11:40:41 -050096 . = RESET_VECTOR_ADDRESS + 0x4;
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -050097
Peter Tyser430445f2009-10-07 11:45:00 -050098 /*
99 * Make sure that the bss segment isn't linked at 0x0, otherwise its
100 * address won't be updated during relocation fixups. Note that
101 * this is a temporary fix. Code to dynamically the fixup the bss
102 * location will be added in the future. When the bss relocation
103 * fixup code is present this workaround should be removed.
104 */
105#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
106 . |= 0x10;
107#endif
Ying Zhang0d4f5442013-05-20 14:07:23 +0800108#endif
Peter Tyser430445f2009-10-07 11:45:00 -0500109
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -0500110 __bss_start = .;
111 .bss (NOLOAD) :
112 {
Peter Tyser1047c162010-09-29 14:05:56 -0500113 *(.sbss*)
114 *(.bss*)
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -0500115 *(COMMON)
Pali Rohár18209f72022-06-16 14:19:44 +0200116 }
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -0500117
118 . = ALIGN(4);
Simon Glassed70c8f2013-03-14 06:54:53 +0000119 __bss_end = . ;
Srikanth Srinivasan949a2d52009-04-03 15:36:13 -0500120 PROVIDE (end = .);
121}