blob: 40469d1be0906794406fb09c2bb4f029c943d95b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Daniel Schwierzecke8d31552016-01-09 18:34:14 +01002/*
3 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
4 * Copyright (C) 1995, 1996 Paul M. Antoine
5 * Copyright (C) 1998 Ulf Carlsson
6 * Copyright (C) 1999 Silicon Graphics, Inc.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
9 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
10 * Copyright (C) 2014, Imagination Technologies Ltd.
Daniel Schwierzecke8d31552016-01-09 18:34:14 +010011 */
12
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Simon Glass6b9f0102020-05-10 11:40:06 -060014#include <asm/ptrace.h>
Tom Rinid6e2acc2023-10-12 19:03:58 -040015#include <config.h>
Simon Glass63334482019-11-14 12:57:39 -070016#include <cpu_func.h>
Simon Glassf11478f2019-12-28 10:45:07 -070017#include <hang.h>
Simon Glass537ecc92019-11-14 12:57:48 -070018#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060019#include <log.h>
Daniel Schwierzecke8d31552016-01-09 18:34:14 +010020#include <asm/mipsregs.h>
21#include <asm/addrspace.h>
22#include <asm/system.h>
Tom Riniabb9a042024-05-18 20:20:43 -060023#include <asm/u-boot.h>
Daniel Schwierzecke8d31552016-01-09 18:34:14 +010024
25DECLARE_GLOBAL_DATA_PTR;
26
developer5cbbd712020-04-21 09:28:25 +020027static unsigned long saved_ebase;
28
Daniel Schwierzecke8d31552016-01-09 18:34:14 +010029static void show_regs(const struct pt_regs *regs)
30{
31 const int field = 2 * sizeof(unsigned long);
32 unsigned int cause = regs->cp0_cause;
33 unsigned int exccode;
34 int i;
35
36 /*
37 * Saved main processor registers
38 */
39 for (i = 0; i < 32; ) {
40 if ((i % 4) == 0)
41 printf("$%2d :", i);
42 if (i == 0)
43 printf(" %0*lx", field, 0UL);
44 else if (i == 26 || i == 27)
45 printf(" %*s", field, "");
46 else
47 printf(" %0*lx", field, regs->regs[i]);
48
49 i++;
50 if ((i % 4) == 0)
51 puts("\n");
52 }
53
54 printf("Hi : %0*lx\n", field, regs->hi);
55 printf("Lo : %0*lx\n", field, regs->lo);
56
57 /*
58 * Saved cp0 registers
59 */
60 printf("epc : %0*lx (text %0*lx)\n", field, regs->cp0_epc,
61 field, regs->cp0_epc - gd->reloc_off);
62 printf("ra : %0*lx (text %0*lx)\n", field, regs->regs[31],
63 field, regs->regs[31] - gd->reloc_off);
64
65 printf("Status: %08x\n", (uint32_t) regs->cp0_status);
66
67 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
68 printf("Cause : %08x (ExcCode %02x)\n", cause, exccode);
69
70 if (1 <= exccode && exccode <= 5)
71 printf("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
72
73 printf("PrId : %08x\n", read_c0_prid());
74}
75
76void do_reserved(const struct pt_regs *regs)
77{
78 puts("\nOoops:\n");
79 show_regs(regs);
80 hang();
81}
82
83void do_ejtag_debug(const struct pt_regs *regs)
84{
85 const int field = 2 * sizeof(unsigned long);
86 unsigned long depc;
87 unsigned int debug;
88
89 depc = read_c0_depc();
90 debug = read_c0_debug();
91
92 printf("SDBBP EJTAG debug exception: c0_depc = %0*lx, DEBUG = %08x\n",
93 field, depc, debug);
94}
95
96static void set_handler(unsigned long offset, void *addr, unsigned long size)
97{
98 unsigned long ebase = gd->irq_sp;
99
100 memcpy((void *)(ebase + offset), addr, size);
101 flush_cache(ebase + offset, size);
102}
103
Ovidiu Panait2c823912020-11-28 10:43:18 +0200104static void trap_init(ulong reloc_addr)
Daniel Schwierzecke8d31552016-01-09 18:34:14 +0100105{
106 unsigned long ebase = gd->irq_sp;
107
108 set_handler(0x180, &except_vec3_generic, 0x80);
109 set_handler(0x280, &except_vec_ejtag_debug, 0x80);
110
developer5cbbd712020-04-21 09:28:25 +0200111 saved_ebase = read_c0_ebase() & 0xfffff000;
112
Stefan Roesefb79cbd2020-05-14 11:59:06 +0200113 /* Set WG bit on Octeon to enable writing to bits 63:30 */
114 if (IS_ENABLED(CONFIG_ARCH_OCTEON))
Daniel Schwierzecke4ccb472020-07-12 01:46:18 +0200115 ebase |= MIPS_EBASE_WG;
Stefan Roesefb79cbd2020-05-14 11:59:06 +0200116
Daniel Schwierzecke8d31552016-01-09 18:34:14 +0100117 write_c0_ebase(ebase);
118 clear_c0_status(ST0_BEV);
119 execution_hazard_barrier();
120}
developer5cbbd712020-04-21 09:28:25 +0200121
122void trap_restore(void)
123{
124 set_c0_status(ST0_BEV);
125 execution_hazard_barrier();
126
127#ifdef CONFIG_OVERRIDE_EXCEPTION_VECTOR_BASE
128 write_c0_ebase(CONFIG_NEW_EXCEPTION_VECTOR_BASE & 0xfffff000);
129#else
130 write_c0_ebase(saved_ebase);
131#endif
132
133 clear_c0_status(ST0_BEV);
134 execution_hazard_barrier();
135}
Ovidiu Panait2c823912020-11-28 10:43:18 +0200136
137int arch_initr_trap(void)
138{
Tom Rinibb4dd962022-11-16 13:10:37 -0500139 trap_init(CFG_SYS_SDRAM_BASE);
Ovidiu Panait2c823912020-11-28 10:43:18 +0200140
141 return 0;
142}