blob: 6954e6c6a17f68df968eaa0efb343a0781481718 [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2022 Nuvoton Technology Corp.
4 */
5
Tom Riniabb9a042024-05-18 20:20:43 -06006#include <common.h>
Jim Liu147c0002022-09-27 16:45:15 +08007#include <asm/io.h>
8#include <asm/arch/gcr.h>
9#include <asm/arch/rst.h>
10
11void reset_cpu(void)
12{
13 /* Generate a watchdog0 reset */
14 writel(WTCR_WTR | WTCR_WTRE | WTCR_WTE, WTCR0_REG);
15
16 while (1)
17 ;
18}
19
20void reset_misc(void)
21{
22 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
23
24 clrbits_le32(&gcr->intcr2, INTCR2_WDC);
25}
26
27int npcm_get_reset_status(void)
28{
29 struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
30 u32 val;
31
32 val = readl(&gcr->ressr);
33 if (!val)
34 val = readl(&gcr->intcr2);
35
36 return val & RST_STS_MASK;
37}