blob: 862f0ca4793d5f5776bd6e2ac94c55bc1dc12620 [file] [log] [blame]
developerff9f2d42022-09-09 19:59:11 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
developer87bf1bc2023-07-19 17:15:41 +08007#include <fdtdec.h>
developerff9f2d42022-09-09 19:59:11 +08008#include <init.h>
9#include <asm/armv8/mmu.h>
10#include <asm/system.h>
11#include <asm/global_data.h>
Tom Riniabb9a042024-05-18 20:20:43 -060012#include <asm/u-boot.h>
Tom Rini5ba346a2022-10-28 20:27:08 -040013#include <linux/sizes.h>
developerff9f2d42022-09-09 19:59:11 +080014
15DECLARE_GLOBAL_DATA_PTR;
16
17int dram_init(void)
18{
developer87bf1bc2023-07-19 17:15:41 +080019 int ret;
20
21 ret = fdtdec_setup_mem_size_base();
22 if (ret)
23 return ret;
24
25 gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G);
developerff9f2d42022-09-09 19:59:11 +080026
27 return 0;
28}
29
Tom Rinie3b32642023-03-09 11:22:07 -050030void reset_cpu(void)
developerff9f2d42022-09-09 19:59:11 +080031{
32 psci_system_reset();
33}
34
35static struct mm_region mt7981_mem_map[] = {
36 {
37 /* DDR */
38 .virt = 0x40000000UL,
39 .phys = 0x40000000UL,
40 .size = 0x80000000UL,
41 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
42 }, {
43 .virt = 0x00000000UL,
44 .phys = 0x00000000UL,
45 .size = 0x40000000UL,
46 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
47 PTE_BLOCK_NON_SHARE |
48 PTE_BLOCK_PXN | PTE_BLOCK_UXN
49 }, {
50 0,
51 }
52};
53
54struct mm_region *mem_map = mt7981_mem_map;