Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Steve Rae | 45f2c70 | 2016-06-02 15:10:56 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2013 Broadcom Corporation. |
Steve Rae | 45f2c70 | 2016-06-02 15:10:56 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
Tom Rini | abb9a04 | 2024-05-18 20:20:43 -0600 | [diff] [blame] | 6 | #include <common.h> |
Steve Rae | 45f2c70 | 2016-06-02 15:10:56 -0700 | [diff] [blame] | 7 | #include <asm/io.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 8 | #include <linux/errno.h> |
Steve Rae | 45f2c70 | 2016-06-02 15:10:56 -0700 | [diff] [blame] | 9 | #include <asm/arch/sysmap.h> |
| 10 | #include <asm/kona-common/clk.h> |
| 11 | #include "clk-core.h" |
| 12 | |
| 13 | /* Enable appropriate clocks for a BSC/I2C port */ |
| 14 | int clk_bsc_enable(void *base) |
| 15 | { |
| 16 | int ret; |
| 17 | char *bscstr, *apbstr; |
| 18 | |
| 19 | switch ((u32) base) { |
| 20 | case PMU_BSC_BASE_ADDR: |
| 21 | /* PMU clock is always enabled */ |
| 22 | return 0; |
| 23 | case BSC1_BASE_ADDR: |
| 24 | bscstr = "bsc1_clk"; |
| 25 | apbstr = "bsc1_apb_clk"; |
| 26 | break; |
| 27 | case BSC2_BASE_ADDR: |
| 28 | bscstr = "bsc2_clk"; |
| 29 | apbstr = "bsc2_apb_clk"; |
| 30 | break; |
| 31 | case BSC3_BASE_ADDR: |
| 32 | bscstr = "bsc3_clk"; |
| 33 | apbstr = "bsc3_apb_clk"; |
| 34 | break; |
| 35 | default: |
| 36 | printf("%s: base 0x%p not found\n", __func__, base); |
| 37 | return -EINVAL; |
| 38 | } |
| 39 | |
| 40 | /* Note that the bus clock must be enabled first */ |
| 41 | |
| 42 | ret = clk_get_and_enable(apbstr); |
| 43 | if (ret) |
| 44 | return ret; |
| 45 | |
| 46 | ret = clk_get_and_enable(bscstr); |
| 47 | if (ret) |
| 48 | return ret; |
| 49 | |
| 50 | return 0; |
| 51 | } |