blob: f7ee9dbac3508905b413418c651432a5621738ae [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ryan Mallon50515fa2011-06-05 07:21:22 +00002/*
3 * Bluewater Systems Snapper 9260 and 9G20 modules
4 *
5 * (C) Copyright 2011 Bluewater Systems
6 * Author: Andre Renaud <andre@bluewatersys.com>
7 * Author: Ryan Mallon <ryan@bluewatersys.com>
Ryan Mallon50515fa2011-06-05 07:21:22 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* SoC type is defined in boards.cfg */
14#include <asm/hardware.h>
Alexey Brodkin267d8e22014-02-26 17:47:58 +040015#include <linux/sizes.h>
Ryan Mallon50515fa2011-06-05 07:21:22 +000016
Ryan Mallon50515fa2011-06-05 07:21:22 +000017/* ARM asynchronous clock */
18#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
19#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Ryan Mallon50515fa2011-06-05 07:21:22 +000020
21/* CPU */
Ryan Mallon50515fa2011-06-05 07:21:22 +000022
Ryan Mallon50515fa2011-06-05 07:21:22 +000023/* SDRAM */
Ryan Mallon50515fa2011-06-05 07:21:22 +000024#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
25#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
26#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
27 GENERATED_GBL_DATA_SIZE)
28
29/* Mem test settings */
Ryan Mallon50515fa2011-06-05 07:21:22 +000030
31/* NAND Flash */
Ryan Mallon50515fa2011-06-05 07:21:22 +000032#define CONFIG_SYS_MAX_NAND_DEVICE 1
33#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
34#define CONFIG_SYS_NAND_DBW_8
35#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
36#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
37#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
38#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
39
Ryan Mallon50515fa2011-06-05 07:21:22 +000040/* USB */
41#define CONFIG_USB_ATMEL
Bo Shen4a985df2013-10-21 16:14:00 +080042#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Ryan Mallon50515fa2011-06-05 07:21:22 +000043#define CONFIG_USB_OHCI_NEW
Ryan Mallon50515fa2011-06-05 07:21:22 +000044#define CONFIG_SYS_USB_OHCI_CPU_INIT
45#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
46#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
47#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Ryan Mallon50515fa2011-06-05 07:21:22 +000048
49/* GPIOs and IO expander */
Ryan Mallon50515fa2011-06-05 07:21:22 +000050#define CONFIG_PCA953X
51#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
52#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
53
54/* UARTs/Serial console */
Simon Glass6d20e072014-10-29 13:09:01 -060055#ifndef CONFIG_DM_SERIAL
Ryan Mallon50515fa2011-06-05 07:21:22 +000056#define CONFIG_USART_BASE ATMEL_BASE_DBGU
57#define CONFIG_USART_ID ATMEL_ID_SYS
Simon Glass6d20e072014-10-29 13:09:01 -060058#endif
Ryan Mallon50515fa2011-06-05 07:21:22 +000059
60/* I2C - Bit-bashed */
Ryan Mallon50515fa2011-06-05 07:21:22 +000061#define CONFIG_SOFT_I2C_READ_REPEATED_START
Ryan Mallon50515fa2011-06-05 07:21:22 +000062#define I2C_INIT do { \
63 at91_set_gpio_output(AT91_PIN_PA23, 1); \
64 at91_set_gpio_output(AT91_PIN_PA24, 1); \
65 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
66 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
67 } while (0)
68#define I2C_SOFT_DECLARATIONS
69#define I2C_ACTIVE
70#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1);
71#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23);
72#define I2C_SDA(bit) do { \
73 if (bit) { \
74 at91_set_gpio_input(AT91_PIN_PA23, 1); \
75 } else { \
76 at91_set_gpio_output(AT91_PIN_PA23, 1); \
77 at91_set_gpio_value(AT91_PIN_PA23, bit); \
78 } \
79 } while (0)
80#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
81#define I2C_DELAY udelay(2)
82
83/* Boot options */
Ryan Mallon50515fa2011-06-05 07:21:22 +000084
Ryan Mallon50515fa2011-06-05 07:21:22 +000085/* Environment settings */
Ryan Mallon50515fa2011-06-05 07:21:22 +000086
87/* Console settings */
Ryan Mallon50515fa2011-06-05 07:21:22 +000088
Ryan Mallon50515fa2011-06-05 07:21:22 +000089#endif /* __CONFIG_H */