Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2006 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | |
| 25 | #include <common.h> |
Stefan Roese | 34a64a4 | 2008-03-19 10:23:43 +0100 | [diff] [blame] | 26 | #include <libfdt.h> |
| 27 | #include <fdt_support.h> |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 28 | #include <spd_sdram.h> |
| 29 | #include <ppc4xx_enet.h> |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 30 | #include <miiphy.h> |
Stefan Roese | 34a64a4 | 2008-03-19 10:23:43 +0100 | [diff] [blame] | 31 | #include <asm/processor.h> |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 32 | |
| 33 | DECLARE_GLOBAL_DATA_PTR; |
| 34 | |
| 35 | extern int alpr_fpga_init(void); |
| 36 | |
| 37 | int board_early_init_f (void) |
| 38 | { |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 39 | /*------------------------------------------------------------------------- |
| 40 | * Initialize EBC CONFIG |
| 41 | *-------------------------------------------------------------------------*/ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 42 | mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | |
Stefan Roese | a183188 | 2006-10-07 11:35:25 +0200 | [diff] [blame] | 43 | EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | |
| 44 | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | |
| 45 | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | |
| 46 | EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 47 | |
| 48 | /*-------------------------------------------------------------------- |
| 49 | * Setup the interrupt controller polarities, triggers, etc. |
| 50 | *-------------------------------------------------------------------*/ |
Stefan Roese | 51d6d5d | 2008-06-26 17:36:39 +0200 | [diff] [blame] | 51 | /* |
| 52 | * Because of the interrupt handling rework to handle 440GX interrupts |
| 53 | * with the common code, we needed to change names of the UIC registers. |
| 54 | * Here the new relationship: |
| 55 | * |
| 56 | * U-Boot name 440GX name |
| 57 | * ----------------------- |
| 58 | * UIC0 UICB0 |
| 59 | * UIC1 UIC0 |
| 60 | * UIC2 UIC1 |
| 61 | * UIC3 UIC2 |
| 62 | */ |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 63 | mtdcr (UIC1SR, 0xffffffff); /* clear all */ |
| 64 | mtdcr (UIC1ER, 0x00000000); /* disable all */ |
| 65 | mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ |
| 66 | mtdcr (UIC1PR, 0xfffffe03); /* per manual */ |
| 67 | mtdcr (UIC1TR, 0x01c00000); /* per manual */ |
| 68 | mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ |
| 69 | mtdcr (UIC1SR, 0xffffffff); /* clear all */ |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 70 | |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 71 | mtdcr (UIC2SR, 0xffffffff); /* clear all */ |
| 72 | mtdcr (UIC2ER, 0x00000000); /* disable all */ |
| 73 | mtdcr (UIC2CR, 0x00000000); /* all non-critical */ |
| 74 | mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ |
| 75 | mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ |
| 76 | mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ |
| 77 | mtdcr (UIC2SR, 0xffffffff); /* clear all */ |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 78 | |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 79 | mtdcr (UIC3SR, 0xffffffff); /* clear all */ |
| 80 | mtdcr (UIC3ER, 0x00000000); /* disable all */ |
| 81 | mtdcr (UIC3CR, 0x00000000); /* all non-critical */ |
| 82 | mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ |
| 83 | mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ |
| 84 | mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ |
| 85 | mtdcr (UIC3SR, 0xffffffff); /* clear all */ |
Stefan Roese | 51d6d5d | 2008-06-26 17:36:39 +0200 | [diff] [blame] | 86 | |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 87 | mtdcr (UIC0SR, 0xfc000000); /* clear all */ |
| 88 | mtdcr (UIC0ER, 0x00000000); /* disable all */ |
| 89 | mtdcr (UIC0CR, 0x00000000); /* all non-critical */ |
| 90 | mtdcr (UIC0PR, 0xfc000000); /* */ |
| 91 | mtdcr (UIC0TR, 0x00000000); /* */ |
| 92 | mtdcr (UIC0VR, 0x00000001); /* */ |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 93 | |
Stefan Roese | 1d9192f | 2007-01-06 15:56:13 +0100 | [diff] [blame] | 94 | /* Setup shutdown/SSD empty interrupt as inputs */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 95 | out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); |
| 96 | out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); |
Stefan Roese | 1d9192f | 2007-01-06 15:56:13 +0100 | [diff] [blame] | 97 | |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 98 | /* Setup GPIO/IRQ multiplexing */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 99 | mtsdr(SDR0_PFC0, 0x01a33e00); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 100 | |
| 101 | return 0; |
| 102 | } |
| 103 | |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 104 | int last_stage_init(void) |
| 105 | { |
| 106 | unsigned short reg; |
| 107 | |
| 108 | /* |
| 109 | * Configure LED's of both Marvell 88E1111 PHY's |
| 110 | * |
| 111 | * This has to be done after the 4xx ethernet driver is loaded, |
| 112 | * so "last_stage_init()" is the right place. |
| 113 | */ |
| 114 | miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®); |
| 115 | reg |= 0x0001; |
| 116 | miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg); |
| 117 | miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®); |
| 118 | reg |= 0x0001; |
| 119 | miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg); |
| 120 | |
| 121 | return 0; |
| 122 | } |
| 123 | |
| 124 | static int board_rev(void) |
| 125 | { |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 126 | /* Setup as input */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 127 | out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1)); |
| 128 | out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1)); |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 129 | |
Stefan Roese | 1d9192f | 2007-01-06 15:56:13 +0100 | [diff] [blame] | 130 | return (in32(GPIO0_IR) >> 16) & 0x3; |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 131 | } |
| 132 | |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 133 | int checkboard (void) |
| 134 | { |
| 135 | char *s = getenv ("serial#"); |
| 136 | |
| 137 | printf ("Board: ALPR"); |
| 138 | if (s != NULL) { |
| 139 | puts (", serial# "); |
| 140 | puts (s); |
| 141 | } |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 142 | printf(" (Rev. %d)\n", board_rev()); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 143 | |
| 144 | return (0); |
| 145 | } |
| 146 | |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 147 | /************************************************************************* |
| 148 | * pci_pre_init |
| 149 | * |
| 150 | * This routine is called just prior to registering the hose and gives |
| 151 | * the board the opportunity to check things. Returning a value of zero |
| 152 | * indicates that things are bad & PCI initialization should be aborted. |
| 153 | * |
| 154 | * Different boards may wish to customize the pci controller structure |
| 155 | * (add regions, override default access routines, etc) or perform |
| 156 | * certain pre-initialization actions. |
| 157 | * |
| 158 | ************************************************************************/ |
Stefan Roese | 54ef7fd | 2007-06-25 15:57:39 +0200 | [diff] [blame] | 159 | #if defined(CONFIG_PCI) |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 160 | int pci_pre_init(struct pci_controller * hose ) |
| 161 | { |
| 162 | unsigned long strap; |
| 163 | |
| 164 | /*--------------------------------------------------------------------------+ |
| 165 | * The ocotea board is always configured as the host & requires the |
| 166 | * PCI arbiter to be enabled. |
| 167 | *--------------------------------------------------------------------------*/ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 168 | mfsdr(SDR0_SDSTP1, strap); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 169 | if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ |
| 170 | printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); |
| 171 | return 0; |
| 172 | } |
| 173 | |
| 174 | /* FPGA Init */ |
| 175 | alpr_fpga_init (); |
| 176 | |
| 177 | return 1; |
| 178 | } |
Stefan Roese | 54ef7fd | 2007-06-25 15:57:39 +0200 | [diff] [blame] | 179 | #endif /* defined(CONFIG_PCI) */ |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 180 | |
| 181 | /************************************************************************* |
| 182 | * pci_target_init |
| 183 | * |
| 184 | * The bootstrap configuration provides default settings for the pci |
| 185 | * inbound map (PIM). But the bootstrap config choices are limited and |
| 186 | * may not be sufficient for a given board. |
| 187 | * |
| 188 | ************************************************************************/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 189 | #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 190 | void pci_target_init(struct pci_controller * hose ) |
| 191 | { |
| 192 | /*--------------------------------------------------------------------------+ |
| 193 | * Disable everything |
| 194 | *--------------------------------------------------------------------------*/ |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 195 | out32r( PCIL0_PIM0SA, 0 ); /* disable */ |
| 196 | out32r( PCIL0_PIM1SA, 0 ); /* disable */ |
| 197 | out32r( PCIL0_PIM2SA, 0 ); /* disable */ |
| 198 | out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 199 | |
| 200 | /*--------------------------------------------------------------------------+ |
| 201 | * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping |
| 202 | * options to not support sizes such as 128/256 MB. |
| 203 | *--------------------------------------------------------------------------*/ |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 204 | out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); |
| 205 | out32r( PCIL0_PIM0LAH, 0 ); |
| 206 | out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 207 | |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 208 | out32r( PCIL0_BAR0, 0 ); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 209 | |
| 210 | /*--------------------------------------------------------------------------+ |
| 211 | * Program the board's subsystem id/vendor id |
| 212 | *--------------------------------------------------------------------------*/ |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 213 | out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); |
| 214 | out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 215 | |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 216 | out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 217 | } |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 218 | #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 219 | |
| 220 | /************************************************************************* |
| 221 | * is_pci_host |
| 222 | * |
| 223 | * This routine is called to determine if a pci scan should be |
| 224 | * performed. With various hardware environments (especially cPCI and |
| 225 | * PPMC) it's insufficient to depend on the state of the arbiter enable |
| 226 | * bit in the strap register, or generic host/adapter assumptions. |
| 227 | * |
| 228 | * Rather than hard-code a bad assumption in the general 440 code, the |
| 229 | * 440 pci code requires the board to decide at runtime. |
| 230 | * |
| 231 | * Return 0 for adapter mode, non-zero for host (monarch) mode. |
| 232 | * |
| 233 | * |
| 234 | ************************************************************************/ |
| 235 | #if defined(CONFIG_PCI) |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 236 | |
| 237 | static void wait_for_pci_ready(void) |
| 238 | { |
| 239 | /* |
| 240 | * Configure EREADY as input |
| 241 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 242 | out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY); |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 243 | udelay(1000); |
| 244 | |
| 245 | for (;;) { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 246 | if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY) |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 247 | return; |
| 248 | } |
| 249 | |
| 250 | } |
| 251 | |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 252 | int is_pci_host(struct pci_controller *hose) |
| 253 | { |
Stefan Roese | 2a4a943 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 254 | wait_for_pci_ready(); |
| 255 | return 1; /* return 1 for host controller */ |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 256 | } |
| 257 | #endif /* defined(CONFIG_PCI) */ |
| 258 | |
| 259 | /************************************************************************* |
| 260 | * pci_master_init |
| 261 | * |
| 262 | ************************************************************************/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 263 | #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 264 | void pci_master_init(struct pci_controller *hose) |
| 265 | { |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 266 | /*--------------------------------------------------------------------------+ |
| 267 | | PowerPC440 PCI Master configuration. |
| 268 | | Map PLB/processor addresses to PCI memory space. |
| 269 | | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF |
| 270 | | Use byte reversed out routines to handle endianess. |
| 271 | | Make this region non-prefetchable. |
| 272 | +--------------------------------------------------------------------------*/ |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 273 | out32r( PCIL0_POM0SA, 0 ); /* disable */ |
| 274 | out32r( PCIL0_POM1SA, 0 ); /* disable */ |
| 275 | out32r( PCIL0_POM2SA, 0 ); /* disable */ |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 276 | |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 277 | out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ |
| 278 | out32r(PCIL0_POM0LAH, 0x00000003); /* PMM0 Local Address */ |
| 279 | out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ |
| 280 | out32r(PCIL0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */ |
| 281 | out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 282 | |
Niklaus Giger | 728bd0a | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 283 | out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ |
| 284 | out32r(PCIL0_POM1LAH, 0x00000003); /* PMM0 Local Address */ |
| 285 | out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ |
| 286 | out32r(PCIL0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ |
| 287 | out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 288 | } |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 289 | #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ |
Stefan Roese | 4963968 | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 290 | |
| 291 | #ifdef CONFIG_POST |
| 292 | /* |
| 293 | * Returns 1 if keys pressed to start the power-on long-running tests |
| 294 | * Called from board_init_f(). |
| 295 | */ |
| 296 | int post_hotkeys_pressed(void) |
| 297 | { |
| 298 | |
| 299 | return (ctrlc()); |
| 300 | } |
| 301 | #endif |