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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chander Kashyapbfef54d2011-05-24 20:02:56 +00002/*
3 * Copyright (C) 2011 Samsung Electronics
Chander Kashyapbfef54d2011-05-24 20:02:56 +00004 */
5
6#include <common.h>
Simon Glass37f11622014-10-20 19:48:37 -06007#include <asm/gpio.h>
Chander Kashyapbfef54d2011-05-24 20:02:56 +00008#include <asm/io.h>
9#include <netdev.h>
10#include <asm/arch/cpu.h>
Chander Kashyapbfef54d2011-05-24 20:02:56 +000011#include <asm/arch/mmc.h>
Rajeshwari Shinde99ae9b82013-07-04 12:29:16 +053012#include <asm/arch/periph.h>
13#include <asm/arch/pinmux.h>
Chander Kashyapbfef54d2011-05-24 20:02:56 +000014#include <asm/arch/sromc.h>
15
16DECLARE_GLOBAL_DATA_PTR;
Chander Kashyapbfef54d2011-05-24 20:02:56 +000017
18static void smc9115_pre_init(void)
19{
20 u32 smc_bw_conf, smc_bc_conf;
21
22 /* gpio configuration GPK0CON */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +053023 gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
Chander Kashyapbfef54d2011-05-24 20:02:56 +000024
25 /* Ethernet needs bus width of 16 bits */
26 smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
27 smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F)
28 | SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F)
29 | SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F)
30 | SROMC_BC_PMC(0x0F);
31
32 /* Select and configure the SROMC bank */
33 s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
34}
35
36int board_init(void)
37{
Chander Kashyapbfef54d2011-05-24 20:02:56 +000038 smc9115_pre_init();
39
Chander Kashyapbfef54d2011-05-24 20:02:56 +000040 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
41 return 0;
42}
43
44int dram_init(void)
45{
46 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
47 + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
48 + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
49 + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
50
51 return 0;
52}
53
Simon Glass2f949c32017-03-31 08:40:32 -060054int dram_init_banksize(void)
Chander Kashyapbfef54d2011-05-24 20:02:56 +000055{
56 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
Minkyu Kangd4e645b2015-10-23 15:59:37 +090057 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
Chander Kashyapf5ed2952011-09-20 21:25:02 +000058 PHYS_SDRAM_1_SIZE);
Chander Kashyapbfef54d2011-05-24 20:02:56 +000059 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
Minkyu Kangd4e645b2015-10-23 15:59:37 +090060 gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
Chander Kashyapf5ed2952011-09-20 21:25:02 +000061 PHYS_SDRAM_2_SIZE);
Chander Kashyapbfef54d2011-05-24 20:02:56 +000062 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
Minkyu Kangd4e645b2015-10-23 15:59:37 +090063 gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
Chander Kashyapf5ed2952011-09-20 21:25:02 +000064 PHYS_SDRAM_3_SIZE);
Chander Kashyapbfef54d2011-05-24 20:02:56 +000065 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
Minkyu Kangd4e645b2015-10-23 15:59:37 +090066 gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
Chander Kashyapf5ed2952011-09-20 21:25:02 +000067 PHYS_SDRAM_4_SIZE);
Simon Glass2f949c32017-03-31 08:40:32 -060068
69 return 0;
Chander Kashyapbfef54d2011-05-24 20:02:56 +000070}
71
72int board_eth_init(bd_t *bis)
73{
74 int rc = 0;
75#ifdef CONFIG_SMC911X
76 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
77#endif
78 return rc;
79}
80
81#ifdef CONFIG_DISPLAY_BOARDINFO
82int checkboard(void)
83{
84 printf("\nBoard: SMDKV310\n");
85 return 0;
86}
87#endif
88
Masahiro Yamada0a780172017-05-09 20:31:39 +090089#ifdef CONFIG_MMC
Chander Kashyapbfef54d2011-05-24 20:02:56 +000090int board_mmc_init(bd_t *bis)
91{
92 int i, err;
93
94 /*
95 * MMC2 SD card GPIO:
96 *
97 * GPK2[0] SD_2_CLK(2)
98 * GPK2[1] SD_2_CMD(2)
99 * GPK2[2] SD_2_CDn
100 * GPK2[3:6] SD_2_DATA[0:3](2)
101 */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530102 for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) {
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000103 /* GPK2[0:6] special function 2 */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530104 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000105
106 /* GPK2[0:6] drv 4x */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530107 gpio_set_drv(i, S5P_GPIO_DRV_4X);
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000108
109 /* GPK2[0:1] pull disable */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530110 if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) {
111 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000112 continue;
113 }
114
115 /* GPK2[2:6] pull up */
Akshay Saraswat1376cdd2014-05-13 10:30:14 +0530116 gpio_set_pull(i, S5P_GPIO_PULL_UP);
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000117 }
118 err = s5p_mmc_init(2, 4);
119 return err;
120}
121#endif
Rajeshwari Shinde99ae9b82013-07-04 12:29:16 +0530122
123static int board_uart_init(void)
124{
125 int err;
126
127 err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
128 if (err) {
129 debug("UART0 not configured\n");
130 return err;
131 }
132
133 err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
134 if (err) {
135 debug("UART1 not configured\n");
136 return err;
137 }
138
139 err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
140 if (err) {
141 debug("UART2 not configured\n");
142 return err;
143 }
144
145 err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
146 if (err) {
147 debug("UART3 not configured\n");
148 return err;
149 }
150
151 return 0;
152}
153
154#ifdef CONFIG_BOARD_EARLY_INIT_F
155int board_early_init_f(void)
156{
157 int err;
158 err = board_uart_init();
159 if (err) {
160 debug("UART init failed\n");
161 return err;
162 }
163 return err;
164}
165#endif