blob: fb912654097eacdaecac0bda80a13ea1640f2f4d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +01002/*
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +01005 */
6
Simon Glass0f2af882020-05-10 11:40:05 -06007#include <log.h>
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +01008#include <usb.h>
9#include <errno.h>
10#include <linux/compiler.h>
Simon Glassdbd79542020-05-10 11:40:11 -060011#include <linux/delay.h>
Mateusz Kulikowski3add69e2016-03-31 23:12:23 +020012#include <usb/ehci-ci.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +010014#include <asm/io.h>
15#include <asm/arch/imx-regs.h>
16#include <asm/arch/clock.h>
Lukasz Majewskidbc70f82019-04-04 12:26:52 +020017#include <dm.h>
18#include <power/regulator.h>
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +010019
20#include "ehci.h"
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +010021
22#define MX5_USBOTHER_REGS_OFFSET 0x800
23
24
Benoît Thébaudeaucb109722012-11-13 09:56:15 +000025#define MXC_OTG_OFFSET 0
26#define MXC_H1_OFFSET 0x200
27#define MXC_H2_OFFSET 0x400
Benoît Thébaudeau284a4592012-11-13 09:57:14 +000028#define MXC_H3_OFFSET 0x600
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +010029
30#define MXC_USBCTRL_OFFSET 0
31#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
32#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
33#define MXC_USB_CTRL_1_OFFSET 0x10
34#define MXC_USBH2CTRL_OFFSET 0x14
Benoît Thébaudeau284a4592012-11-13 09:57:14 +000035#define MXC_USBH3CTRL_OFFSET 0x18
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +010036
37/* USB_CTRL */
Benoît Thébaudeaucb109722012-11-13 09:56:15 +000038/* OTG wakeup intr enable */
39#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
40/* OTG power mask */
41#define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
Benoît Thébaudeau17971a92012-11-13 09:57:27 +000042/* OTG power pin polarity */
43#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
Benoît Thébaudeaucb109722012-11-13 09:56:15 +000044/* Host1 ULPI interrupt enable */
45#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
46/* HOST1 wakeup intr enable */
47#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
48/* HOST1 power mask */
49#define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
Benoît Thébaudeau17971a92012-11-13 09:57:27 +000050/* HOST1 power pin polarity */
51#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +010052
53/* USB_PHY_CTRL_FUNC */
Benoît Thébaudeau17971a92012-11-13 09:57:27 +000054/* OTG Polarity of Overcurrent */
55#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
Benoît Thébaudeaucb109722012-11-13 09:56:15 +000056/* OTG Disable Overcurrent Event */
57#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
Benoît Thébaudeau17971a92012-11-13 09:57:27 +000058/* UH1 Polarity of Overcurrent */
59#define MXC_H1_OC_POL_BIT (1 << 6)
Benoît Thébaudeaucb109722012-11-13 09:56:15 +000060/* UH1 Disable Overcurrent Event */
61#define MXC_H1_OC_DIS_BIT (1 << 5)
Benoît Thébaudeau17971a92012-11-13 09:57:27 +000062/* OTG Power Pin Polarity */
63#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +010064
65/* USBH2CTRL */
Benoît Thébaudeau17971a92012-11-13 09:57:27 +000066#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
Benoît Thébaudeau284a4592012-11-13 09:57:14 +000067#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
Benoît Thébaudeaucb109722012-11-13 09:56:15 +000068#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
69#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
70#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
Benoît Thébaudeau17971a92012-11-13 09:57:27 +000071#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +010072
Benoît Thébaudeau284a4592012-11-13 09:57:14 +000073/* USBH3CTRL */
Benoît Thébaudeau17971a92012-11-13 09:57:27 +000074#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
Benoît Thébaudeau284a4592012-11-13 09:57:14 +000075#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
76#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
77#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
Benoît Thébaudeau17971a92012-11-13 09:57:27 +000078#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
Benoît Thébaudeau284a4592012-11-13 09:57:14 +000079
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +010080/* USB_CTRL_1 */
Benoît Thébaudeaucb109722012-11-13 09:56:15 +000081#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +010082
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +010083int mxc_set_usbcontrol(int port, unsigned int flags)
84{
85 unsigned int v;
86 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
87 void __iomem *usbother_base;
88 int ret = 0;
89
90 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
91
92 switch (port) {
93 case 0: /* OTG port */
94 if (flags & MXC_EHCI_INTERNAL_PHY) {
95 v = __raw_readl(usbother_base +
96 MXC_USB_PHY_CTR_FUNC_OFFSET);
Benoît Thébaudeau17971a92012-11-13 09:57:27 +000097 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
98 v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
99 else
100 v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100101 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100102 /* OC/USBPWR is used */
103 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
Benoît Thébaudeau2b2a4152012-11-13 09:56:30 +0000104 else
105 /* OC/USBPWR is not used */
106 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
Benoît Thébaudeau17971a92012-11-13 09:57:27 +0000107#ifdef CONFIG_MX51
108 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
109 v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
110 else
111 v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
112#endif
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100113 __raw_writel(v, usbother_base +
114 MXC_USB_PHY_CTR_FUNC_OFFSET);
115
116 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
Benoît Thébaudeau46a53ab2012-11-13 09:56:59 +0000117#ifdef CONFIG_MX51
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100118 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100119 v &= ~MXC_OTG_UCTRL_OPM_BIT;
Benoît Thébaudeaub7647f32012-11-13 09:56:44 +0000120 else
121 v |= MXC_OTG_UCTRL_OPM_BIT;
Benoît Thébaudeau46a53ab2012-11-13 09:56:59 +0000122#endif
Benoît Thébaudeau17971a92012-11-13 09:57:27 +0000123#ifdef CONFIG_MX53
124 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
125 v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
126 else
127 v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
128#endif
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100129 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
130 }
131 break;
Benoît Thébaudeaucb109722012-11-13 09:56:15 +0000132 case 1: /* Host 1 ULPI */
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100133#ifdef CONFIG_MX51
134 /* The clock for the USBH1 ULPI port will come externally
135 from the PHY. */
136 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
137 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
138 MXC_USB_CTRL_1_OFFSET);
139#endif
140
141 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
Benoît Thébaudeau46a53ab2012-11-13 09:56:59 +0000142#ifdef CONFIG_MX51
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100143 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
Benoît Thébaudeaucb109722012-11-13 09:56:15 +0000144 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100145 else
Benoît Thébaudeaucb109722012-11-13 09:56:15 +0000146 v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
Benoît Thébaudeau46a53ab2012-11-13 09:56:59 +0000147#endif
Benoît Thébaudeau17971a92012-11-13 09:57:27 +0000148#ifdef CONFIG_MX53
149 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
150 v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
151 else
152 v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
153#endif
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100154 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
155
156 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
Benoît Thébaudeau17971a92012-11-13 09:57:27 +0000157 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
158 v |= MXC_H1_OC_POL_BIT;
159 else
160 v &= ~MXC_H1_OC_POL_BIT;
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100161 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
162 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
163 else
164 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
165 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
166
167 break;
168 case 2: /* Host 2 ULPI */
169 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
Benoît Thébaudeau46a53ab2012-11-13 09:56:59 +0000170#ifdef CONFIG_MX51
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100171 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
Benoît Thébaudeaucb109722012-11-13 09:56:15 +0000172 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100173 else
Benoît Thébaudeaucb109722012-11-13 09:56:15 +0000174 v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
Benoît Thébaudeau46a53ab2012-11-13 09:56:59 +0000175#endif
Benoît Thébaudeau284a4592012-11-13 09:57:14 +0000176#ifdef CONFIG_MX53
Benoît Thébaudeau17971a92012-11-13 09:57:27 +0000177 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
178 v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
179 else
180 v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
Benoît Thébaudeau284a4592012-11-13 09:57:14 +0000181 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
182 v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
183 else
184 v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
Benoît Thébaudeau17971a92012-11-13 09:57:27 +0000185 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
186 v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
187 else
188 v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
Benoît Thébaudeau284a4592012-11-13 09:57:14 +0000189#endif
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100190 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
191 break;
Benoît Thébaudeau284a4592012-11-13 09:57:14 +0000192#ifdef CONFIG_MX53
193 case 3: /* Host 3 ULPI */
194 v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
Benoît Thébaudeau17971a92012-11-13 09:57:27 +0000195 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
196 v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
197 else
198 v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
Benoît Thébaudeau284a4592012-11-13 09:57:14 +0000199 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
200 v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
201 else
202 v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
Benoît Thébaudeau17971a92012-11-13 09:57:27 +0000203 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
204 v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
205 else
206 v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
Benoît Thébaudeau284a4592012-11-13 09:57:14 +0000207 __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
208 break;
209#endif
Wolfgang Grandeggerd17f2d22011-11-11 14:03:36 +0100210 }
211
212 return ret;
213}
214
Benoît Thébaudeau98023c12012-11-13 09:58:35 +0000215int __weak board_ehci_hcd_init(int port)
Marek Vasutde09b792011-11-24 05:14:00 +0100216{
Benoît Thébaudeau98023c12012-11-13 09:58:35 +0000217 return 0;
Marek Vasutde09b792011-11-24 05:14:00 +0100218}
219
Benoît Thébaudeau98023c12012-11-13 09:58:35 +0000220void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
221{
222}
Marek Vasutde09b792011-11-24 05:14:00 +0100223
Simon Glassdc9f3ed2015-03-25 12:22:27 -0600224__weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
225 uint32_t *reg)
226{
227 mdelay(50);
228}
229
Lukasz Majewskidbc70f82019-04-04 12:26:52 +0200230struct ehci_mx5_priv_data {
231 struct ehci_ctrl ctrl;
232 struct usb_ehci *ehci;
233 struct udevice *vbus_supply;
234 enum usb_init_type init_type;
235 int portnr;
236};
237
238static const struct ehci_ops mx5_ehci_ops = {
239 .powerup_fixup = mx5_ehci_powerup_fixup,
240};
241
Simon Glassaad29ae2020-12-03 16:55:21 -0700242static int ehci_usb_of_to_plat(struct udevice *dev)
Lukasz Majewskidbc70f82019-04-04 12:26:52 +0200243{
Simon Glassb75b15b2020-12-03 16:55:23 -0700244 struct usb_plat *plat = dev_get_plat(dev);
Lukasz Majewskidbc70f82019-04-04 12:26:52 +0200245 const char *mode;
246
247 mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
248 if (mode) {
249 if (strcmp(mode, "peripheral") == 0)
250 plat->init_type = USB_INIT_DEVICE;
251 else if (strcmp(mode, "host") == 0)
252 plat->init_type = USB_INIT_HOST;
253 else
254 return -EINVAL;
255 }
256
257 return 0;
258}
259
260static int ehci_usb_probe(struct udevice *dev)
261{
Simon Glassb75b15b2020-12-03 16:55:23 -0700262 struct usb_plat *plat = dev_get_plat(dev);
Masahiro Yamada1096ae12020-07-17 14:36:46 +0900263 struct usb_ehci *ehci = dev_read_addr_ptr(dev);
Lukasz Majewskidbc70f82019-04-04 12:26:52 +0200264 struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
265 enum usb_init_type type = plat->init_type;
266 struct ehci_hccr *hccr;
267 struct ehci_hcor *hcor;
268 int ret;
269
270 set_usboh3_clk();
271 enable_usboh3_clk(true);
272 set_usb_phy_clk();
273 enable_usb_phy1_clk(true);
274 enable_usb_phy2_clk(true);
275 mdelay(1);
276
277 priv->ehci = ehci;
Simon Glass75e534b2020-12-16 21:20:07 -0700278 priv->portnr = dev_seq(dev);
Lukasz Majewskidbc70f82019-04-04 12:26:52 +0200279 priv->init_type = type;
280
281 ret = device_get_supply_regulator(dev, "vbus-supply",
282 &priv->vbus_supply);
283 if (ret)
284 debug("%s: No vbus supply\n", dev->name);
285
286 if (!ret && priv->vbus_supply) {
287 ret = regulator_set_enable(priv->vbus_supply,
288 (type == USB_INIT_DEVICE) ?
289 false : true);
290 if (ret) {
291 puts("Error enabling VBUS supply\n");
292 return ret;
293 }
294 }
295
296 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
297 hcor = (struct ehci_hcor *)((uint32_t)hccr +
298 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
299 setbits_le32(&ehci->usbmode, CM_HOST);
300
Tom Rinib9796e82022-12-04 10:04:56 -0500301 __raw_writel(CFG_MXC_USB_PORTSC, &ehci->portsc);
Lukasz Majewskidbc70f82019-04-04 12:26:52 +0200302 setbits_le32(&ehci->portsc, USB_EN);
303
Tom Rinib9796e82022-12-04 10:04:56 -0500304 mxc_set_usbcontrol(priv->portnr, CFG_MXC_USB_FLAGS);
Lukasz Majewskidbc70f82019-04-04 12:26:52 +0200305 mdelay(10);
306
307 return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
308 priv->init_type);
309}
310
311static const struct udevice_id mx5_usb_ids[] = {
312 { .compatible = "fsl,imx53-usb" },
313 { }
314};
315
316U_BOOT_DRIVER(usb_mx5) = {
317 .name = "ehci_mx5",
318 .id = UCLASS_USB,
319 .of_match = mx5_usb_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700320 .of_to_plat = ehci_usb_of_to_plat,
Lukasz Majewskidbc70f82019-04-04 12:26:52 +0200321 .probe = ehci_usb_probe,
322 .remove = ehci_deregister,
323 .ops = &ehci_usb_ops,
Simon Glassb75b15b2020-12-03 16:55:23 -0700324 .plat_auto = sizeof(struct usb_plat),
Simon Glass8a2b47f2020-12-03 16:55:17 -0700325 .priv_auto = sizeof(struct ehci_mx5_priv_data),
Lukasz Majewskidbc70f82019-04-04 12:26:52 +0200326 .flags = DM_FLAG_ALLOC_PRIV_DMA,
327};