Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015-2016 Marvell International Ltd. |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 6 | #include <fdtdec.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 7 | #include <log.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 8 | #include <asm/global_data.h> |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 9 | #include <asm/io.h> |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 10 | #include <asm/ptrace.h> |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 11 | #include <asm/arch/cpu.h> |
| 12 | #include <asm/arch/soc.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 13 | #include <linux/delay.h> |
Tom Rini | 98cc7b2 | 2024-05-01 19:31:07 -0600 | [diff] [blame] | 14 | #include <linux/errno.h> |
Simon Glass | bdd5f81 | 2023-09-14 18:21:46 -0600 | [diff] [blame] | 15 | #include <linux/printk.h> |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 16 | |
Marek BehĂșn | 19ce44c | 2018-08-17 12:58:51 +0200 | [diff] [blame] | 17 | #include "comphy_core.h" |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 18 | #include "sata.h" |
| 19 | #include "utmi_phy.h" |
| 20 | |
| 21 | DECLARE_GLOBAL_DATA_PTR; |
| 22 | |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 23 | /* Firmware related definitions used for SMC calls */ |
| 24 | #define MV_SIP_COMPHY_POWER_ON 0x82000001 |
| 25 | #define MV_SIP_COMPHY_POWER_OFF 0x82000002 |
| 26 | #define MV_SIP_COMPHY_PLL_LOCK 0x82000003 |
Grzegorz Jaszczyk | a8e6b49 | 2018-04-03 16:59:12 +0200 | [diff] [blame] | 27 | #define MV_SIP_COMPHY_XFI_TRAIN 0x82000004 |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 28 | |
Michal Simek | 50fa118 | 2023-05-17 09:17:16 +0200 | [diff] [blame] | 29 | /* Used to distinguish between different possible callers (U-Boot/Linux) */ |
Igal Liberman | 67d1a3f | 2020-10-18 17:11:13 +0300 | [diff] [blame] | 30 | #define COMPHY_CALLER_UBOOT (0x1 << 21) |
| 31 | |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 32 | #define COMPHY_FW_MODE_FORMAT(mode) ((mode) << 12) |
| 33 | #define COMPHY_FW_FORMAT(mode, idx, speeds) \ |
| 34 | (((mode) << 12) | ((idx) << 8) | ((speeds) << 2)) |
Grzegorz Jaszczyk | c42b5a3 | 2020-10-18 17:11:12 +0300 | [diff] [blame] | 35 | |
| 36 | #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ |
Igal Liberman | 67d1a3f | 2020-10-18 17:11:13 +0300 | [diff] [blame] | 37 | (COMPHY_CALLER_UBOOT | ((pcie_width) << 18) | \ |
| 38 | ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds)) |
Grzegorz Jaszczyk | c42b5a3 | 2020-10-18 17:11:12 +0300 | [diff] [blame] | 39 | |
Denis Odintsov | fcbb255 | 2021-09-15 15:45:31 +0200 | [diff] [blame] | 40 | /* Invert polarity are bits 1-0 of the mode */ |
| 41 | #define COMPHY_FW_SATA_FORMAT(mode, invert) \ |
| 42 | ((invert) | COMPHY_FW_MODE_FORMAT(mode)) |
| 43 | |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 44 | #define COMPHY_SATA_MODE 0x1 |
| 45 | #define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */ |
| 46 | #define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */ |
| 47 | #define COMPHY_USB3H_MODE 0x4 |
| 48 | #define COMPHY_USB3D_MODE 0x5 |
| 49 | #define COMPHY_PCIE_MODE 0x6 |
| 50 | #define COMPHY_RXAUI_MODE 0x7 |
| 51 | #define COMPHY_XFI_MODE 0x8 |
| 52 | #define COMPHY_SFI_MODE 0x9 |
| 53 | #define COMPHY_USB3_MODE 0xa |
| 54 | #define COMPHY_AP_MODE 0xb |
| 55 | |
| 56 | /* Comphy unit index macro */ |
| 57 | #define COMPHY_UNIT_ID0 0 |
| 58 | #define COMPHY_UNIT_ID1 1 |
| 59 | #define COMPHY_UNIT_ID2 2 |
| 60 | #define COMPHY_UNIT_ID3 3 |
| 61 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 62 | struct utmi_phy_data { |
Grzegorz Jaszczyk | 85bb206 | 2019-02-27 15:35:58 +0100 | [diff] [blame] | 63 | void __iomem *utmi_pll_addr; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 64 | void __iomem *utmi_base_addr; |
| 65 | void __iomem *usb_cfg_addr; |
| 66 | void __iomem *utmi_cfg_addr; |
| 67 | u32 utmi_phy_port; |
| 68 | }; |
| 69 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 70 | static u32 polling_with_timeout(void __iomem *addr, u32 val, |
| 71 | u32 mask, unsigned long usec_timout) |
| 72 | { |
| 73 | u32 data; |
| 74 | |
| 75 | do { |
| 76 | udelay(1); |
| 77 | data = readl(addr) & mask; |
| 78 | } while (data != val && --usec_timout > 0); |
| 79 | |
| 80 | if (usec_timout == 0) |
| 81 | return data; |
| 82 | |
| 83 | return 0; |
| 84 | } |
| 85 | |
Grzegorz Jaszczyk | a8e6b49 | 2018-04-03 16:59:12 +0200 | [diff] [blame] | 86 | static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr, |
| 87 | u32 lane, u32 mode) |
Igal Liberman | 6795a66 | 2021-03-23 11:57:57 +0100 | [diff] [blame] | 88 | { |
Grzegorz Jaszczyk | a8e6b49 | 2018-04-03 16:59:12 +0200 | [diff] [blame] | 89 | struct pt_regs pregs = {0}; |
Igal Liberman | 6795a66 | 2021-03-23 11:57:57 +0100 | [diff] [blame] | 90 | |
Grzegorz Jaszczyk | a8e6b49 | 2018-04-03 16:59:12 +0200 | [diff] [blame] | 91 | pregs.regs[0] = function_id; |
| 92 | pregs.regs[1] = (unsigned long)comphy_base_addr; |
| 93 | pregs.regs[2] = lane; |
| 94 | pregs.regs[3] = mode; |
Igal Liberman | 6795a66 | 2021-03-23 11:57:57 +0100 | [diff] [blame] | 95 | |
Grzegorz Jaszczyk | a8e6b49 | 2018-04-03 16:59:12 +0200 | [diff] [blame] | 96 | smc_call(&pregs); |
Igal Liberman | 6795a66 | 2021-03-23 11:57:57 +0100 | [diff] [blame] | 97 | |
Grzegorz Jaszczyk | a8e6b49 | 2018-04-03 16:59:12 +0200 | [diff] [blame] | 98 | /* |
| 99 | * TODO: Firmware return 0 on success, temporary map it to u-boot |
| 100 | * convention, but after all comphy will be reworked the convention in |
| 101 | * u-boot should be change and this conversion removed |
| 102 | */ |
| 103 | return pregs.regs[0] ? 0 : 1; |
Igal Liberman | 6795a66 | 2021-03-23 11:57:57 +0100 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | /* This function performs RX training for all FFE possible values. |
| 107 | * We get the result for each FFE and eventually the best FFE will |
| 108 | * be used and set to the HW. |
| 109 | * |
| 110 | * Return '1' on succsess. |
| 111 | * Return '0' on failure. |
| 112 | */ |
| 113 | int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg, |
| 114 | u32 lane) |
| 115 | { |
Igal Liberman | 6795a66 | 2021-03-23 11:57:57 +0100 | [diff] [blame] | 116 | int ret; |
Igal Liberman | d7297e3 | 2018-05-14 11:20:54 +0300 | [diff] [blame] | 117 | u32 type = ptr_chip_cfg->comphy_map_data[lane].type; |
Igal Liberman | 6795a66 | 2021-03-23 11:57:57 +0100 | [diff] [blame] | 118 | |
| 119 | debug_enter(); |
| 120 | |
Igal Liberman | d7297e3 | 2018-05-14 11:20:54 +0300 | [diff] [blame] | 121 | if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) { |
Igal Liberman | 6795a66 | 2021-03-23 11:57:57 +0100 | [diff] [blame] | 122 | pr_err("Comphy %d isn't configured to SFI\n", lane); |
| 123 | return 0; |
| 124 | } |
| 125 | |
Grzegorz Jaszczyk | a8e6b49 | 2018-04-03 16:59:12 +0200 | [diff] [blame] | 126 | /* Mode is not relevant for xfi training */ |
| 127 | ret = comphy_smc(MV_SIP_COMPHY_XFI_TRAIN, |
| 128 | ptr_chip_cfg->comphy_base_addr, lane, 0); |
Igal Liberman | 6795a66 | 2021-03-23 11:57:57 +0100 | [diff] [blame] | 129 | |
| 130 | debug_exit(); |
| 131 | |
| 132 | return ret; |
| 133 | } |
| 134 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 135 | static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 136 | void __iomem *comphy_base_addr, int cp_index, |
| 137 | u32 type) |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 138 | { |
| 139 | u32 mask, data, i, ret = 1; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 140 | void __iomem *sata_base = NULL; |
| 141 | int sata_node = -1; /* Set to -1 in order to read the first sata node */ |
| 142 | |
| 143 | debug_enter(); |
| 144 | |
| 145 | /* |
| 146 | * Assumption - each CP has only one SATA controller |
| 147 | * Calling fdt_node_offset_by_compatible first time (with sata_node = -1 |
| 148 | * will return the first node always. |
| 149 | * In order to parse each CPs SATA node, fdt_node_offset_by_compatible |
| 150 | * must be called again (according to the CP id) |
| 151 | */ |
Igal Liberman | c8855ce | 2017-04-24 18:45:32 +0300 | [diff] [blame] | 152 | for (i = 0; i < (cp_index + 1); i++) |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 153 | sata_node = fdt_node_offset_by_compatible( |
| 154 | gd->fdt_blob, sata_node, "marvell,armada-8k-ahci"); |
| 155 | |
| 156 | if (sata_node == 0) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 157 | pr_err("SATA node not found in FDT\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 158 | return 0; |
| 159 | } |
| 160 | |
| 161 | sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 162 | gd->fdt_blob, sata_node, "reg", 0, NULL, true); |
| 163 | if (sata_base == NULL) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 164 | pr_err("SATA address not found in FDT\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 165 | return 0; |
| 166 | } |
| 167 | |
| 168 | debug("SATA address found in FDT %p\n", sata_base); |
| 169 | |
| 170 | debug("stage: MAC configuration - power down comphy\n"); |
| 171 | /* |
| 172 | * MAC configuration powe down comphy use indirect address for |
| 173 | * vendor spesific SATA control register |
| 174 | */ |
| 175 | reg_set(sata_base + SATA3_VENDOR_ADDRESS, |
| 176 | SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, |
| 177 | SATA3_VENDOR_ADDR_MASK); |
| 178 | /* SATA 0 power down */ |
| 179 | mask = SATA3_CTRL_SATA0_PD_MASK; |
| 180 | data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET; |
| 181 | /* SATA 1 power down */ |
| 182 | mask |= SATA3_CTRL_SATA1_PD_MASK; |
| 183 | data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET; |
| 184 | /* SATA SSU disable */ |
| 185 | mask |= SATA3_CTRL_SATA1_ENABLE_MASK; |
| 186 | data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET; |
| 187 | /* SATA port 1 disable */ |
| 188 | mask |= SATA3_CTRL_SATA_SSU_MASK; |
| 189 | data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; |
| 190 | reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); |
| 191 | |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 192 | ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, comphy_base_addr, lane, type); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 193 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 194 | /* |
| 195 | * MAC configuration power up comphy - power up PLL/TX/RX |
| 196 | * use indirect address for vendor spesific SATA control register |
| 197 | */ |
| 198 | reg_set(sata_base + SATA3_VENDOR_ADDRESS, |
| 199 | SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, |
| 200 | SATA3_VENDOR_ADDR_MASK); |
| 201 | /* SATA 0 power up */ |
| 202 | mask = SATA3_CTRL_SATA0_PD_MASK; |
| 203 | data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET; |
| 204 | /* SATA 1 power up */ |
| 205 | mask |= SATA3_CTRL_SATA1_PD_MASK; |
| 206 | data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET; |
| 207 | /* SATA SSU enable */ |
| 208 | mask |= SATA3_CTRL_SATA1_ENABLE_MASK; |
| 209 | data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET; |
| 210 | /* SATA port 1 enable */ |
| 211 | mask |= SATA3_CTRL_SATA_SSU_MASK; |
| 212 | data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET; |
| 213 | reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); |
| 214 | |
| 215 | /* MBUS request size and interface select register */ |
| 216 | reg_set(sata_base + SATA3_VENDOR_ADDRESS, |
| 217 | SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET, |
| 218 | SATA3_VENDOR_ADDR_MASK); |
| 219 | /* Mbus regret enable */ |
| 220 | reg_set(sata_base + SATA3_VENDOR_DATA, |
| 221 | 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK); |
| 222 | |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 223 | ret = comphy_smc(MV_SIP_COMPHY_PLL_LOCK, comphy_base_addr, lane, type); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 224 | |
| 225 | debug_exit(); |
| 226 | return ret; |
| 227 | } |
| 228 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 229 | static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr, |
| 230 | void __iomem *usb_cfg_addr, |
| 231 | void __iomem *utmi_cfg_addr, |
| 232 | u32 utmi_phy_port) |
| 233 | { |
| 234 | u32 mask, data; |
| 235 | |
| 236 | debug_enter(); |
| 237 | debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n", |
| 238 | utmi_index); |
| 239 | /* Power down UTMI PHY */ |
| 240 | reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET, |
| 241 | UTMI_PHY_CFG_PU_MASK); |
| 242 | |
| 243 | /* |
| 244 | * If UTMI connected to USB Device, configure mux prior to PHY init |
| 245 | * (Device can be connected to UTMI0 or to UTMI1) |
| 246 | */ |
Stefan Roese | b781f57 | 2017-04-24 18:45:23 +0300 | [diff] [blame] | 247 | if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) { |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 248 | debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", |
| 249 | utmi_index); |
| 250 | /* USB3 Device UTMI enable */ |
| 251 | mask = UTMI_USB_CFG_DEVICE_EN_MASK; |
| 252 | data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET; |
| 253 | /* USB3 Device UTMI MUX */ |
| 254 | mask |= UTMI_USB_CFG_DEVICE_MUX_MASK; |
| 255 | data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET; |
| 256 | reg_set(usb_cfg_addr, data, mask); |
| 257 | } |
| 258 | |
| 259 | /* Set Test suspendm mode */ |
| 260 | mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK; |
| 261 | data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET; |
| 262 | /* Enable Test UTMI select */ |
| 263 | mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK; |
| 264 | data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET; |
| 265 | reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); |
| 266 | |
| 267 | /* Wait for UTMI power down */ |
| 268 | mdelay(1); |
| 269 | |
| 270 | debug_exit(); |
| 271 | return; |
| 272 | } |
| 273 | |
Grzegorz Jaszczyk | 85bb206 | 2019-02-27 15:35:58 +0100 | [diff] [blame] | 274 | static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr, |
| 275 | void __iomem *utmi_base_addr, |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 276 | void __iomem *usb_cfg_addr, |
| 277 | void __iomem *utmi_cfg_addr, |
| 278 | u32 utmi_phy_port) |
| 279 | { |
| 280 | u32 mask, data; |
| 281 | |
| 282 | debug_exit(); |
| 283 | debug("stage: Configure UTMI PHY %d registers\n", utmi_index); |
| 284 | /* Reference Clock Divider Select */ |
| 285 | mask = UTMI_PLL_CTRL_REFDIV_MASK; |
| 286 | data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET; |
| 287 | /* Feedback Clock Divider Select - 90 for 25Mhz*/ |
| 288 | mask |= UTMI_PLL_CTRL_FBDIV_MASK; |
| 289 | data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET; |
| 290 | /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ |
| 291 | mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; |
| 292 | data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; |
Grzegorz Jaszczyk | 85bb206 | 2019-02-27 15:35:58 +0100 | [diff] [blame] | 293 | reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 294 | |
| 295 | /* Impedance Calibration Threshold Setting */ |
Grzegorz Jaszczyk | 390c11c | 2019-03-14 13:00:53 +0100 | [diff] [blame] | 296 | mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK; |
| 297 | data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET; |
| 298 | reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask); |
| 299 | |
| 300 | /* Start Impedance and PLL Calibration */ |
| 301 | mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK; |
| 302 | data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET); |
| 303 | mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK; |
| 304 | data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET); |
| 305 | reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 306 | |
| 307 | /* Set LS TX driver strength coarse control */ |
Igal Liberman | 32af216 | 2017-04-30 20:16:55 +0300 | [diff] [blame] | 308 | mask = UTMI_TX_CH_CTRL_AMP_MASK; |
| 309 | data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; |
Grzegorz Jaszczyk | 390c11c | 2019-03-14 13:00:53 +0100 | [diff] [blame] | 310 | mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; |
| 311 | data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; |
| 312 | mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; |
| 313 | data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 314 | reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); |
| 315 | |
| 316 | /* Enable SQ */ |
| 317 | mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; |
Grzegorz Jaszczyk | 390c11c | 2019-03-14 13:00:53 +0100 | [diff] [blame] | 318 | data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 319 | /* Enable analog squelch detect */ |
| 320 | mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; |
Grzegorz Jaszczyk | 390c11c | 2019-03-14 13:00:53 +0100 | [diff] [blame] | 321 | data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; |
| 322 | mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK; |
| 323 | data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 324 | reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); |
| 325 | |
| 326 | /* Set External squelch calibration number */ |
| 327 | mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK; |
| 328 | data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET; |
| 329 | /* Enable the External squelch calibration */ |
| 330 | mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK; |
| 331 | data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET; |
| 332 | reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); |
| 333 | |
| 334 | /* Set Control VDAT Reference Voltage - 0.325V */ |
| 335 | mask = UTMI_CHGDTC_CTRL_VDAT_MASK; |
| 336 | data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET; |
| 337 | /* Set Control VSRC Reference Voltage - 0.6V */ |
| 338 | mask |= UTMI_CHGDTC_CTRL_VSRC_MASK; |
| 339 | data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET; |
| 340 | reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); |
| 341 | |
| 342 | debug_exit(); |
| 343 | return; |
| 344 | } |
| 345 | |
Grzegorz Jaszczyk | 85bb206 | 2019-02-27 15:35:58 +0100 | [diff] [blame] | 346 | static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_pll_addr, |
| 347 | void __iomem *utmi_base_addr, |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 348 | void __iomem *usb_cfg_addr, |
| 349 | void __iomem *utmi_cfg_addr, u32 utmi_phy_port) |
| 350 | { |
| 351 | u32 data, mask, ret = 1; |
| 352 | void __iomem *addr; |
| 353 | |
| 354 | debug_enter(); |
| 355 | debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n", |
| 356 | utmi_index); |
| 357 | /* Power UP UTMI PHY */ |
| 358 | reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET, |
| 359 | UTMI_PHY_CFG_PU_MASK); |
| 360 | /* Disable Test UTMI select */ |
| 361 | reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, |
| 362 | 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET, |
| 363 | UTMI_CTRL_STATUS0_TEST_SEL_MASK); |
| 364 | |
| 365 | debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n"); |
Grzegorz Jaszczyk | 85bb206 | 2019-02-27 15:35:58 +0100 | [diff] [blame] | 366 | addr = utmi_pll_addr + UTMI_CALIB_CTRL_REG; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 367 | data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; |
| 368 | mask = data; |
| 369 | data = polling_with_timeout(addr, data, mask, 100); |
| 370 | if (data != 0) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 371 | pr_err("Impedance calibration is not done\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 372 | debug("Read from reg = %p - value = 0x%x\n", addr, data); |
| 373 | ret = 0; |
| 374 | } |
| 375 | |
| 376 | data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK; |
| 377 | mask = data; |
| 378 | data = polling_with_timeout(addr, data, mask, 100); |
| 379 | if (data != 0) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 380 | pr_err("PLL calibration is not done\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 381 | debug("Read from reg = %p - value = 0x%x\n", addr, data); |
| 382 | ret = 0; |
| 383 | } |
| 384 | |
Grzegorz Jaszczyk | 85bb206 | 2019-02-27 15:35:58 +0100 | [diff] [blame] | 385 | addr = utmi_pll_addr + UTMI_PLL_CTRL_REG; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 386 | data = UTMI_PLL_CTRL_PLL_RDY_MASK; |
| 387 | mask = data; |
| 388 | data = polling_with_timeout(addr, data, mask, 100); |
| 389 | if (data != 0) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 390 | pr_err("PLL is not ready\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 391 | debug("Read from reg = %p - value = 0x%x\n", addr, data); |
| 392 | ret = 0; |
| 393 | } |
| 394 | |
| 395 | if (ret) |
| 396 | debug("Passed\n"); |
| 397 | else |
| 398 | debug("\n"); |
| 399 | |
| 400 | debug_exit(); |
| 401 | return ret; |
| 402 | } |
| 403 | |
| 404 | /* |
| 405 | * comphy_utmi_phy_init initialize the UTMI PHY |
| 406 | * the init split in 3 parts: |
| 407 | * 1. Power down transceiver and PLL |
| 408 | * 2. UTMI PHY configure |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 409 | * 3. Power up transceiver and PLL |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 410 | * Note: - Power down/up should be once for both UTMI PHYs |
| 411 | * - comphy_dedicated_phys_init call this function if at least there is |
| 412 | * one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is |
| 413 | * legal |
| 414 | */ |
| 415 | static void comphy_utmi_phy_init(u32 utmi_phy_count, |
| 416 | struct utmi_phy_data *cp110_utmi_data) |
| 417 | { |
| 418 | u32 i; |
| 419 | |
| 420 | debug_enter(); |
| 421 | /* UTMI Power down */ |
| 422 | for (i = 0; i < utmi_phy_count; i++) { |
| 423 | comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr, |
| 424 | cp110_utmi_data[i].usb_cfg_addr, |
| 425 | cp110_utmi_data[i].utmi_cfg_addr, |
| 426 | cp110_utmi_data[i].utmi_phy_port); |
| 427 | } |
| 428 | /* PLL Power down */ |
| 429 | debug("stage: UTMI PHY power down PLL\n"); |
| 430 | for (i = 0; i < utmi_phy_count; i++) { |
| 431 | reg_set(cp110_utmi_data[i].usb_cfg_addr, |
| 432 | 0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); |
| 433 | } |
| 434 | /* UTMI configure */ |
| 435 | for (i = 0; i < utmi_phy_count; i++) { |
Grzegorz Jaszczyk | 85bb206 | 2019-02-27 15:35:58 +0100 | [diff] [blame] | 436 | comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_pll_addr, |
| 437 | cp110_utmi_data[i].utmi_base_addr, |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 438 | cp110_utmi_data[i].usb_cfg_addr, |
| 439 | cp110_utmi_data[i].utmi_cfg_addr, |
| 440 | cp110_utmi_data[i].utmi_phy_port); |
| 441 | } |
| 442 | /* UTMI Power up */ |
| 443 | for (i = 0; i < utmi_phy_count; i++) { |
Grzegorz Jaszczyk | 85bb206 | 2019-02-27 15:35:58 +0100 | [diff] [blame] | 444 | if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_pll_addr, |
| 445 | cp110_utmi_data[i].utmi_base_addr, |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 446 | cp110_utmi_data[i].usb_cfg_addr, |
| 447 | cp110_utmi_data[i].utmi_cfg_addr, |
| 448 | cp110_utmi_data[i].utmi_phy_port)) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 449 | pr_err("Failed to initialize UTMI PHY %d\n", i); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 450 | continue; |
| 451 | } |
| 452 | printf("UTMI PHY %d initialized to ", i); |
Stefan Roese | b781f57 | 2017-04-24 18:45:23 +0300 | [diff] [blame] | 453 | if (cp110_utmi_data[i].utmi_phy_port == |
| 454 | UTMI_PHY_TO_USB3_DEVICE0) |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 455 | printf("USB Device\n"); |
| 456 | else |
| 457 | printf("USB Host%d\n", |
| 458 | cp110_utmi_data[i].utmi_phy_port); |
| 459 | } |
| 460 | /* PLL Power up */ |
| 461 | debug("stage: UTMI PHY power up PLL\n"); |
| 462 | for (i = 0; i < utmi_phy_count; i++) { |
| 463 | reg_set(cp110_utmi_data[i].usb_cfg_addr, |
| 464 | 0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); |
| 465 | } |
| 466 | |
| 467 | debug_exit(); |
| 468 | return; |
| 469 | } |
| 470 | |
| 471 | /* |
| 472 | * comphy_dedicated_phys_init initialize the dedicated PHYs |
| 473 | * - not muxed SerDes lanes e.g. UTMI PHY |
| 474 | */ |
| 475 | void comphy_dedicated_phys_init(void) |
| 476 | { |
| 477 | struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT]; |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 478 | int node = -1; |
| 479 | int node_idx; |
Grzegorz Jaszczyk | 85bb206 | 2019-02-27 15:35:58 +0100 | [diff] [blame] | 480 | int parent = -1; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 481 | |
| 482 | debug_enter(); |
| 483 | debug("Initialize USB UTMI PHYs\n"); |
| 484 | |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 485 | for (node_idx = 0; node_idx < MAX_UTMI_PHY_COUNT;) { |
| 486 | /* Find the UTMI phy node in device tree */ |
| 487 | node = fdt_node_offset_by_compatible(gd->fdt_blob, node, |
| 488 | "marvell,mvebu-utmi-2.6.0"); |
| 489 | if (node <= 0) |
| 490 | break; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 491 | |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 492 | /* check if node is enabled */ |
| 493 | if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) |
| 494 | continue; |
| 495 | |
Grzegorz Jaszczyk | 85bb206 | 2019-02-27 15:35:58 +0100 | [diff] [blame] | 496 | parent = fdt_parent_offset(gd->fdt_blob, node); |
| 497 | if (parent <= 0) |
| 498 | break; |
| 499 | |
| 500 | /* get base address of UTMI PLL */ |
| 501 | cp110_utmi_data[node_idx].utmi_pll_addr = |
| 502 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 503 | gd->fdt_blob, parent, "reg", 0, NULL, true); |
| 504 | if (!cp110_utmi_data[node_idx].utmi_pll_addr) { |
| 505 | pr_err("UTMI PHY PLL address is invalid\n"); |
| 506 | continue; |
| 507 | } |
| 508 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 509 | /* get base address of UTMI phy */ |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 510 | cp110_utmi_data[node_idx].utmi_base_addr = |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 511 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 512 | gd->fdt_blob, node, "reg", 0, NULL, true); |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 513 | if (!cp110_utmi_data[node_idx].utmi_base_addr) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 514 | pr_err("UTMI PHY base address is invalid\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 515 | continue; |
| 516 | } |
| 517 | |
| 518 | /* get usb config address */ |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 519 | cp110_utmi_data[node_idx].usb_cfg_addr = |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 520 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 521 | gd->fdt_blob, node, "reg", 1, NULL, true); |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 522 | if (!cp110_utmi_data[node_idx].usb_cfg_addr) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 523 | pr_err("UTMI PHY base address is invalid\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 524 | continue; |
| 525 | } |
| 526 | |
| 527 | /* get UTMI config address */ |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 528 | cp110_utmi_data[node_idx].utmi_cfg_addr = |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 529 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 530 | gd->fdt_blob, node, "reg", 2, NULL, true); |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 531 | if (!cp110_utmi_data[node_idx].utmi_cfg_addr) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 532 | pr_err("UTMI PHY base address is invalid\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 533 | continue; |
| 534 | } |
| 535 | |
| 536 | /* |
| 537 | * get the port number (to check if the utmi connected to |
| 538 | * host/device) |
| 539 | */ |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 540 | cp110_utmi_data[node_idx].utmi_phy_port = fdtdec_get_int( |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 541 | gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 542 | if (cp110_utmi_data[node_idx].utmi_phy_port == |
| 543 | UTMI_PHY_INVALID) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 544 | pr_err("UTMI PHY port type is invalid\n"); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 545 | continue; |
| 546 | } |
| 547 | |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 548 | /* count valid UTMI unit */ |
| 549 | node_idx++; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 550 | } |
| 551 | |
Omri Itach | 561930c | 2017-04-06 12:54:16 +0300 | [diff] [blame] | 552 | if (node_idx > 0) |
| 553 | comphy_utmi_phy_init(node_idx, cp110_utmi_data); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 554 | |
| 555 | debug_exit(); |
| 556 | } |
| 557 | |
Pali RohĂĄr | 04c9347 | 2021-11-26 14:57:13 +0100 | [diff] [blame] | 558 | int comphy_cp110_init_serdes_map(int node, struct chip_serdes_phy_config *cfg) |
| 559 | { |
| 560 | int lane, subnode; |
| 561 | |
| 562 | cfg->comphy_lanes_count = fdtdec_get_int(gd->fdt_blob, node, |
| 563 | "max-lanes", 0); |
| 564 | if (cfg->comphy_lanes_count <= 0) { |
| 565 | printf("comphy max lanes is wrong\n"); |
| 566 | return -EINVAL; |
| 567 | } |
| 568 | |
| 569 | cfg->comphy_mux_bitcount = fdtdec_get_int(gd->fdt_blob, node, |
| 570 | "mux-bitcount", 0); |
| 571 | if (cfg->comphy_mux_bitcount <= 0) { |
| 572 | printf("comphy mux bit count is wrong\n"); |
| 573 | return -EINVAL; |
| 574 | } |
| 575 | |
| 576 | cfg->comphy_mux_lane_order = fdtdec_locate_array(gd->fdt_blob, node, |
| 577 | "mux-lane-order", |
| 578 | cfg->comphy_lanes_count); |
| 579 | |
| 580 | lane = 0; |
| 581 | fdt_for_each_subnode(subnode, gd->fdt_blob, node) { |
| 582 | /* Skip disabled ports */ |
| 583 | if (!fdtdec_get_is_enabled(gd->fdt_blob, subnode)) |
| 584 | continue; |
| 585 | |
| 586 | cfg->comphy_map_data[lane].type = |
| 587 | fdtdec_get_int(gd->fdt_blob, subnode, "phy-type", |
| 588 | COMPHY_TYPE_INVALID); |
| 589 | |
| 590 | if (cfg->comphy_map_data[lane].type == COMPHY_TYPE_INVALID) { |
| 591 | printf("no phy type for lane %d, setting lane as unconnected\n", |
| 592 | lane + 1); |
| 593 | continue; |
| 594 | } |
| 595 | |
| 596 | cfg->comphy_map_data[lane].speed = |
| 597 | fdtdec_get_int(gd->fdt_blob, subnode, "phy-speed", |
| 598 | COMPHY_SPEED_INVALID); |
| 599 | |
| 600 | cfg->comphy_map_data[lane].invert = |
| 601 | fdtdec_get_int(gd->fdt_blob, subnode, "phy-invert", |
| 602 | COMPHY_POLARITY_NO_INVERT); |
| 603 | |
| 604 | cfg->comphy_map_data[lane].clk_src = |
| 605 | fdtdec_get_bool(gd->fdt_blob, subnode, "clk-src"); |
| 606 | |
| 607 | cfg->comphy_map_data[lane].end_point = |
| 608 | fdtdec_get_bool(gd->fdt_blob, subnode, "end_point"); |
| 609 | |
| 610 | lane++; |
| 611 | } |
| 612 | |
| 613 | return 0; |
| 614 | } |
| 615 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 616 | int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, |
| 617 | struct comphy_map *serdes_map) |
| 618 | { |
| 619 | struct comphy_map *ptr_comphy_map; |
| 620 | void __iomem *comphy_base_addr, *hpipe_base_addr; |
Igal Liberman | d009fee | 2018-05-09 18:50:29 +0300 | [diff] [blame] | 621 | u32 comphy_max_count, lane, id, ret = 0; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 622 | u32 pcie_width = 0; |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 623 | u32 mode; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 624 | |
| 625 | debug_enter(); |
| 626 | |
| 627 | comphy_max_count = ptr_chip_cfg->comphy_lanes_count; |
| 628 | comphy_base_addr = ptr_chip_cfg->comphy_base_addr; |
| 629 | hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; |
| 630 | |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 631 | /* Check if the first 4 lanes configured as By-4 */ |
| 632 | for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; |
| 633 | lane++, ptr_comphy_map++) { |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 634 | if (ptr_comphy_map->type != COMPHY_TYPE_PEX0) |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 635 | break; |
| 636 | pcie_width++; |
| 637 | } |
| 638 | |
| 639 | for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count; |
| 640 | lane++, ptr_comphy_map++) { |
| 641 | debug("Initialize serdes number %d\n", lane); |
| 642 | debug("Serdes type = 0x%x\n", ptr_comphy_map->type); |
| 643 | if (lane == 4) { |
| 644 | /* |
| 645 | * PCIe lanes above the first 4 lanes, can be only |
| 646 | * by1 |
| 647 | */ |
| 648 | pcie_width = 1; |
| 649 | } |
| 650 | switch (ptr_comphy_map->type) { |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 651 | case COMPHY_TYPE_UNCONNECTED: |
Igal Liberman | d622f8e | 2018-11-19 09:58:32 +0200 | [diff] [blame] | 652 | mode = COMPHY_TYPE_UNCONNECTED | COMPHY_CALLER_UBOOT; |
Christine Gharzuzi | c63fa15 | 2018-05-23 12:10:36 +0300 | [diff] [blame] | 653 | ret = comphy_smc(MV_SIP_COMPHY_POWER_OFF, |
| 654 | ptr_chip_cfg->comphy_base_addr, |
Igal Liberman | d622f8e | 2018-11-19 09:58:32 +0200 | [diff] [blame] | 655 | lane, mode); |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 656 | case COMPHY_TYPE_IGNORE: |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 657 | continue; |
| 658 | break; |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 659 | case COMPHY_TYPE_PEX0: |
| 660 | case COMPHY_TYPE_PEX1: |
| 661 | case COMPHY_TYPE_PEX2: |
| 662 | case COMPHY_TYPE_PEX3: |
Grzegorz Jaszczyk | c42b5a3 | 2020-10-18 17:11:12 +0300 | [diff] [blame] | 663 | mode = COMPHY_FW_PCIE_FORMAT(pcie_width, |
| 664 | ptr_comphy_map->clk_src, |
| 665 | COMPHY_PCIE_MODE, |
| 666 | ptr_comphy_map->speed); |
| 667 | ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, |
| 668 | ptr_chip_cfg->comphy_base_addr, lane, |
| 669 | mode); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 670 | break; |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 671 | case COMPHY_TYPE_SATA0: |
| 672 | case COMPHY_TYPE_SATA1: |
Denis Odintsov | fcbb255 | 2021-09-15 15:45:31 +0200 | [diff] [blame] | 673 | mode = COMPHY_FW_SATA_FORMAT(COMPHY_SATA_MODE, |
| 674 | serdes_map[lane].invert); |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 675 | ret = comphy_sata_power_up(lane, hpipe_base_addr, |
| 676 | comphy_base_addr, |
| 677 | ptr_chip_cfg->cp_index, |
| 678 | mode); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 679 | break; |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 680 | case COMPHY_TYPE_USB3_HOST0: |
| 681 | case COMPHY_TYPE_USB3_HOST1: |
Grzegorz Jaszczyk | e165970 | 2018-03-29 12:30:20 +0200 | [diff] [blame] | 682 | mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3H_MODE); |
| 683 | ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, |
| 684 | ptr_chip_cfg->comphy_base_addr, lane, |
| 685 | mode); |
| 686 | break; |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 687 | case COMPHY_TYPE_USB3_DEVICE: |
Grzegorz Jaszczyk | e165970 | 2018-03-29 12:30:20 +0200 | [diff] [blame] | 688 | mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3D_MODE); |
| 689 | ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, |
| 690 | ptr_chip_cfg->comphy_base_addr, lane, |
| 691 | mode); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 692 | break; |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 693 | case COMPHY_TYPE_SGMII0: |
| 694 | case COMPHY_TYPE_SGMII1: |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 695 | case COMPHY_TYPE_SGMII2: |
Igal Liberman | d009fee | 2018-05-09 18:50:29 +0300 | [diff] [blame] | 696 | /* Calculate SGMII ID */ |
| 697 | id = ptr_comphy_map->type - COMPHY_TYPE_SGMII0; |
| 698 | |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 699 | if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 700 | debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", |
| 701 | lane); |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 702 | ptr_comphy_map->speed = COMPHY_SPEED_1_25G; |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 703 | } |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 704 | |
Igal Liberman | d009fee | 2018-05-09 18:50:29 +0300 | [diff] [blame] | 705 | mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, id, |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 706 | ptr_comphy_map->speed); |
| 707 | ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, |
| 708 | ptr_chip_cfg->comphy_base_addr, lane, |
| 709 | mode); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 710 | break; |
Igal Liberman | d7297e3 | 2018-05-14 11:20:54 +0300 | [diff] [blame] | 711 | case COMPHY_TYPE_SFI0: |
| 712 | case COMPHY_TYPE_SFI1: |
| 713 | /* Calculate SFI id */ |
| 714 | id = ptr_comphy_map->type - COMPHY_TYPE_SFI0; |
| 715 | mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id, |
Grzegorz Jaszczyk | 7928a8e | 2020-10-18 17:11:11 +0300 | [diff] [blame] | 716 | ptr_comphy_map->speed); |
| 717 | ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, |
Igal Liberman | d7297e3 | 2018-05-14 11:20:54 +0300 | [diff] [blame] | 718 | ptr_chip_cfg->comphy_base_addr, lane, mode); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 719 | break; |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 720 | case COMPHY_TYPE_RXAUI0: |
| 721 | case COMPHY_TYPE_RXAUI1: |
Grzegorz Jaszczyk | beb4a91 | 2018-03-27 12:52:24 +0200 | [diff] [blame] | 722 | mode = COMPHY_FW_MODE_FORMAT(COMPHY_RXAUI_MODE); |
| 723 | ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, |
| 724 | ptr_chip_cfg->comphy_base_addr, lane, |
| 725 | mode); |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 726 | break; |
| 727 | default: |
| 728 | debug("Unknown SerDes type, skip initialize SerDes %d\n", |
| 729 | lane); |
| 730 | break; |
| 731 | } |
| 732 | if (ret == 0) { |
| 733 | /* |
Stefan Roese | 4fbca01 | 2017-04-24 18:45:25 +0300 | [diff] [blame] | 734 | * If interface wans't initialized, set the lane to |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 735 | * COMPHY_TYPE_UNCONNECTED state. |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 736 | */ |
Igal Liberman | ffd5d2f | 2017-04-26 15:40:00 +0300 | [diff] [blame] | 737 | ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED; |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 738 | pr_err("PLL is not locked - Failed to initialize lane %d\n", |
Stefan Roese | 648391c | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 739 | lane); |
| 740 | } |
| 741 | } |
| 742 | |
| 743 | debug_exit(); |
| 744 | return 0; |
| 745 | } |