blob: 34f4a919656e66b78ffeaa8f5ffb5496531796a0 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peter Korsgaard85ec2db2012-10-18 01:21:09 +00002/*
3 * board.c
4 *
5 * Board functions for TI AM335X based boards
6 *
Nishanth Menoneaa39c62023-11-01 15:56:03 -05007 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
Peter Korsgaard85ec2db2012-10-18 01:21:09 +00008 */
9
Tom Rinid7247db2024-04-30 20:43:02 -060010#include <config.h>
Lokesh Vutla2fe7c792017-04-26 13:37:08 +053011#include <dm.h>
Simon Glass79fd2142019-08-01 09:46:43 -060012#include <env.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000013#include <errno.h>
Amjad Ouled-Ameur4d797722021-10-29 16:08:17 +020014#include <hang.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060015#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -070016#include <init.h>
Simon Glass9bc15642020-02-03 07:36:16 -070017#include <malloc.h>
Simon Glass274e0b02020-05-10 11:39:56 -060018#include <net.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000019#include <spl.h>
Lokesh Vutlaabb44e62016-05-16 11:47:29 +053020#include <serial.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000021#include <asm/arch/cpu.h>
22#include <asm/arch/hardware.h>
23#include <asm/arch/omap.h>
24#include <asm/arch/ddr_defs.h>
25#include <asm/arch/clock.h>
Lokesh Vutla0d144f52016-05-16 11:47:26 +053026#include <asm/arch/clk_synthesizer.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000027#include <asm/arch/gpio.h>
28#include <asm/arch/mmc_host_def.h>
29#include <asm/arch/sys_proto.h>
Steve Kipiszbe9b6f82013-07-18 15:13:03 -040030#include <asm/arch/mem.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060031#include <asm/global_data.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000032#include <asm/io.h>
33#include <asm/emif.h>
34#include <asm/gpio.h>
Semen Protsenkoa8cb0222017-06-02 18:00:00 +030035#include <asm/omap_common.h>
Lokesh Vutla2fe7c792017-04-26 13:37:08 +053036#include <asm/omap_mmc.h>
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000037#include <i2c.h>
38#include <miiphy.h>
39#include <cpsw.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060040#include <linux/bitops.h>
Amjad Ouled-Ameur4d797722021-10-29 16:08:17 +020041#include <linux/compiler.h>
Simon Glassdbd79542020-05-10 11:40:11 -060042#include <linux/delay.h>
Tom Rini52437072013-08-30 16:28:46 -040043#include <power/tps65217.h>
44#include <power/tps65910.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060045#include <env_internal.h>
Tom Rini303bfe82013-10-01 12:32:04 -040046#include <watchdog.h>
Nishanth Menon2afa70d2016-02-24 12:30:55 -060047#include "../common/board_detect.h"
Kory Maincent169bf972021-05-04 19:31:30 +020048#include "../common/cape_detect.h"
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000049#include "board.h"
50
51DECLARE_GLOBAL_DATA_PTR;
52
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000053/* GPIO that controls power to DDR on EVM-SK */
Lokesh Vutla0d144f52016-05-16 11:47:26 +053054#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
55#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
56#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
57#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
58#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
59#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
60#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
Roger Quadrosbcb4ee82016-08-24 15:35:50 +030061#define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
62#define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000063
64static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
65
Roger Quadrosbcb4ee82016-08-24 15:35:50 +030066#define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
67#define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
68
69#define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
70#define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
71
72#define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
73#define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
74
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000075/*
76 * Read header information from EEPROM into global structure.
77 */
Lokesh Vutla93e0f5b2016-10-14 10:35:25 +053078#ifdef CONFIG_TI_I2C_BOARD_DETECT
79void do_board_detect(void)
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000080{
Lokesh Vutla93e0f5b2016-10-14 10:35:25 +053081 enable_i2c0_pin_mux();
Kory Maincent4c1a71d2021-05-04 19:31:29 +020082 enable_i2c2_pin_mux();
Simon Glass4df67572017-05-12 21:09:55 -060083 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
84 CONFIG_EEPROM_CHIP_ADDRESS))
Lokesh Vutla93e0f5b2016-10-14 10:35:25 +053085 printf("ti_i2c_eeprom_init failed\n");
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000086}
Lokesh Vutla93e0f5b2016-10-14 10:35:25 +053087#endif
Peter Korsgaard85ec2db2012-10-18 01:21:09 +000088
Lokesh Vutlaabb44e62016-05-16 11:47:29 +053089#ifndef CONFIG_DM_SERIAL
90struct serial_device *default_serial_console(void)
91{
92 if (board_is_icev2())
93 return &eserial4_device;
94 else
95 return &eserial1_device;
96}
97#endif
98
Tom Rinie1e85442021-08-27 21:18:30 -040099#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000100static const struct ddr_data ddr2_data = {
Tom Rini7f50a572014-07-07 21:40:16 -0400101 .datardsratio0 = MT47H128M16RT25E_RD_DQS,
102 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
103 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000104};
105
106static const struct cmd_control ddr2_cmd_ctrl_data = {
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000107 .cmd0csratio = MT47H128M16RT25E_RATIO,
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000108
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000109 .cmd1csratio = MT47H128M16RT25E_RATIO,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000110
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000111 .cmd2csratio = MT47H128M16RT25E_RATIO,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000112};
113
114static const struct emif_regs ddr2_emif_reg_data = {
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000115 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
116 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
117 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
118 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
119 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
120 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000121};
122
Jyri Sarha8d2998b2016-12-09 12:29:13 +0200123static const struct emif_regs ddr2_evm_emif_reg_data = {
124 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
125 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
126 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
127 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
128 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
129 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
130 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
131};
132
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000133static const struct ddr_data ddr3_data = {
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000134 .datardsratio0 = MT41J128MJT125_RD_DQS,
135 .datawdsratio0 = MT41J128MJT125_WR_DQS,
136 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
137 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000138};
139
Tom Rini385bc752013-03-21 04:30:02 +0000140static const struct ddr_data ddr3_beagleblack_data = {
141 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
142 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
143 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
144 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
Tom Rini385bc752013-03-21 04:30:02 +0000145};
146
Jeff Lance7c03a222013-01-14 05:32:20 +0000147static const struct ddr_data ddr3_evm_data = {
148 .datardsratio0 = MT41J512M8RH125_RD_DQS,
149 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
150 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
151 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
Jeff Lance7c03a222013-01-14 05:32:20 +0000152};
153
Lokesh Vutla5837b902016-05-16 11:47:24 +0530154static const struct ddr_data ddr3_icev2_data = {
155 .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
156 .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
157 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
158 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
159};
160
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000161static const struct cmd_control ddr3_cmd_ctrl_data = {
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000162 .cmd0csratio = MT41J128MJT125_RATIO,
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000163 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000164
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000165 .cmd1csratio = MT41J128MJT125_RATIO,
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000166 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000167
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000168 .cmd2csratio = MT41J128MJT125_RATIO,
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000169 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000170};
171
Tom Rini385bc752013-03-21 04:30:02 +0000172static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
173 .cmd0csratio = MT41K256M16HA125E_RATIO,
Tom Rini385bc752013-03-21 04:30:02 +0000174 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
175
176 .cmd1csratio = MT41K256M16HA125E_RATIO,
Tom Rini385bc752013-03-21 04:30:02 +0000177 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
178
179 .cmd2csratio = MT41K256M16HA125E_RATIO,
Tom Rini385bc752013-03-21 04:30:02 +0000180 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
181};
182
Jeff Lance7c03a222013-01-14 05:32:20 +0000183static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
184 .cmd0csratio = MT41J512M8RH125_RATIO,
Jeff Lance7c03a222013-01-14 05:32:20 +0000185 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
186
187 .cmd1csratio = MT41J512M8RH125_RATIO,
Jeff Lance7c03a222013-01-14 05:32:20 +0000188 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
189
190 .cmd2csratio = MT41J512M8RH125_RATIO,
Jeff Lance7c03a222013-01-14 05:32:20 +0000191 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
192};
193
Lokesh Vutla5837b902016-05-16 11:47:24 +0530194static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
195 .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
196 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
197
198 .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
199 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
200
201 .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
202 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
203};
204
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000205static struct emif_regs ddr3_emif_reg_data = {
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000206 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
207 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
208 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
209 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
210 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
211 .zq_config = MT41J128MJT125_ZQ_CFG,
Vaibhav Hiremathc30d57b2013-03-14 21:11:16 +0000212 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
213 PHY_EN_DYN_PWRDN,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000214};
Jeff Lance7c03a222013-01-14 05:32:20 +0000215
Tom Rini385bc752013-03-21 04:30:02 +0000216static struct emif_regs ddr3_beagleblack_emif_reg_data = {
217 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
218 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
219 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
220 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
221 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
Jyri Sarha8d2998b2016-12-09 12:29:13 +0200222 .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
Tom Rini385bc752013-03-21 04:30:02 +0000223 .zq_config = MT41K256M16HA125E_ZQ_CFG,
224 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
225};
226
Jeff Lance7c03a222013-01-14 05:32:20 +0000227static struct emif_regs ddr3_evm_emif_reg_data = {
228 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
229 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
230 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
231 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
232 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
Jyri Sarha8d2998b2016-12-09 12:29:13 +0200233 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
Jeff Lance7c03a222013-01-14 05:32:20 +0000234 .zq_config = MT41J512M8RH125_ZQ_CFG,
Vaibhav Hiremathc30d57b2013-03-14 21:11:16 +0000235 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
236 PHY_EN_DYN_PWRDN,
Jeff Lance7c03a222013-01-14 05:32:20 +0000237};
Peter Korsgaardeb204db2013-05-13 08:36:30 +0000238
Lokesh Vutla5837b902016-05-16 11:47:24 +0530239static struct emif_regs ddr3_icev2_emif_reg_data = {
240 .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
241 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
242 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
243 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
244 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
245 .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
246 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
247 PHY_EN_DYN_PWRDN,
248};
249
Peter Korsgaardeb204db2013-05-13 08:36:30 +0000250#ifdef CONFIG_SPL_OS_BOOT
251int spl_start_uboot(void)
252{
Simon Glassf4d60392021-08-08 12:20:12 -0600253#ifdef CONFIG_SPL_SERIAL
Peter Korsgaardeb204db2013-05-13 08:36:30 +0000254 /* break into full u-boot on 'c' */
Tom Rini810b5812014-03-28 12:03:38 -0400255 if (serial_tstc() && serial_getc() == 'c')
256 return 1;
Alex Kiernandf0df672018-04-19 04:32:53 +0000257#endif
Tom Rini810b5812014-03-28 12:03:38 -0400258
259#ifdef CONFIG_SPL_ENV_SUPPORT
260 env_init();
Simon Glass17539572017-08-03 12:22:07 -0600261 env_load();
Simon Glass22c34c22017-08-03 12:22:13 -0600262 if (env_get_yesno("boot_os") != 1)
Tom Rini810b5812014-03-28 12:03:38 -0400263 return 1;
264#endif
265
266 return 0;
Peter Korsgaardeb204db2013-05-13 08:36:30 +0000267}
268#endif
269
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530270const struct dpll_params *get_dpll_ddr_params(void)
Tom Rini52437072013-08-30 16:28:46 -0400271{
Lokesh Vutla6302e532017-05-05 12:59:10 +0530272 int ind = get_sys_clk_index();
273
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530274 if (board_is_evm_sk())
Lokesh Vutla6302e532017-05-05 12:59:10 +0530275 return &dpll_ddr3_303MHz[ind];
Jason Kridnerb56b5b32018-03-07 05:40:41 -0500276 else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
Lokesh Vutla6302e532017-05-05 12:59:10 +0530277 return &dpll_ddr3_400MHz[ind];
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530278 else if (board_is_evm_15_or_later())
Lokesh Vutla6302e532017-05-05 12:59:10 +0530279 return &dpll_ddr3_303MHz[ind];
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530280 else
Lokesh Vutla6302e532017-05-05 12:59:10 +0530281 return &dpll_ddr2_266MHz[ind];
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530282}
Tom Rini52437072013-08-30 16:28:46 -0400283
Lokesh Vutla6302e532017-05-05 12:59:10 +0530284static u8 bone_not_connected_to_ac_power(void)
285{
286 if (board_is_bone()) {
287 uchar pmic_status_reg;
288 if (tps65217_reg_read(TPS65217_STATUS,
289 &pmic_status_reg))
290 return 1;
291 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
292 puts("No AC power, switching to default OPP\n");
293 return 1;
294 }
295 }
296 return 0;
297}
298
299const struct dpll_params *get_dpll_mpu_params(void)
300{
301 int ind = get_sys_clk_index();
302 int freq = am335x_get_efuse_mpu_max_freq(cdev);
303
304 if (bone_not_connected_to_ac_power())
305 freq = MPUPLL_M_600;
306
Jason Kridnerb56b5b32018-03-07 05:40:41 -0500307 if (board_is_pb() || board_is_bone_lt())
Lokesh Vutla6302e532017-05-05 12:59:10 +0530308 freq = MPUPLL_M_1000;
309
310 switch (freq) {
311 case MPUPLL_M_1000:
312 return &dpll_mpu_opp[ind][5];
313 case MPUPLL_M_800:
314 return &dpll_mpu_opp[ind][4];
315 case MPUPLL_M_720:
316 return &dpll_mpu_opp[ind][3];
317 case MPUPLL_M_600:
318 return &dpll_mpu_opp[ind][2];
319 case MPUPLL_M_500:
320 return &dpll_mpu_opp100;
321 case MPUPLL_M_300:
322 return &dpll_mpu_opp[ind][0];
323 }
324
325 return &dpll_mpu_opp[ind][0];
326}
327
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530328static void scale_vcores_bone(int freq)
329{
330 int usb_cur_lim, mpu_vdd;
Tom Rini52437072013-08-30 16:28:46 -0400331
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530332 /*
333 * Only perform PMIC configurations if board rev > A1
334 * on Beaglebone White
335 */
336 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
337 return;
Tom Rini52437072013-08-30 16:28:46 -0400338
Jean-Jacques Hiblot52a51512018-12-07 14:50:49 +0100339 if (power_tps65217_init(0))
340 return;
Jean-Jacques Hiblot52a51512018-12-07 14:50:49 +0100341
Tom Rini52437072013-08-30 16:28:46 -0400342
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530343 /*
344 * On Beaglebone White we need to ensure we have AC power
345 * before increasing the frequency.
346 */
Lokesh Vutla6302e532017-05-05 12:59:10 +0530347 if (bone_not_connected_to_ac_power())
348 freq = MPUPLL_M_600;
Tom Rini52437072013-08-30 16:28:46 -0400349
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530350 /*
351 * Override what we have detected since we know if we have
352 * a Beaglebone Black it supports 1GHz.
353 */
Jason Kridnerb56b5b32018-03-07 05:40:41 -0500354 if (board_is_pb() || board_is_bone_lt())
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530355 freq = MPUPLL_M_1000;
Tom Rini52437072013-08-30 16:28:46 -0400356
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530357 switch (freq) {
358 case MPUPLL_M_1000:
359 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
360 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
361 break;
362 case MPUPLL_M_800:
363 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
Lokesh Vutlae29609a2017-06-10 13:22:56 +0530364 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530365 break;
366 case MPUPLL_M_720:
367 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
Lokesh Vutlae29609a2017-06-10 13:22:56 +0530368 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530369 break;
370 case MPUPLL_M_600:
371 case MPUPLL_M_500:
372 case MPUPLL_M_300:
Lokesh Vutlae29609a2017-06-10 13:22:56 +0530373 default:
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530374 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
375 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
376 break;
377 }
Steve Kipisz5adac352013-08-14 10:51:31 -0400378
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530379 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
380 TPS65217_POWER_PATH,
381 usb_cur_lim,
382 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
383 puts("tps65217_reg_write failure\n");
Tom Rini52437072013-08-30 16:28:46 -0400384
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530385 /* Set DCDC3 (CORE) voltage to 1.10V */
386 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
387 TPS65217_DCDC_VOLT_SEL_1100MV)) {
388 puts("tps65217_voltage_update failure\n");
389 return;
390 }
Tom Rini52437072013-08-30 16:28:46 -0400391
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530392 /* Set DCDC2 (MPU) voltage */
393 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
394 puts("tps65217_voltage_update failure\n");
395 return;
396 }
Tom Rini52437072013-08-30 16:28:46 -0400397
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530398 /*
399 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
400 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
401 */
402 if (board_is_bone()) {
Tom Rini52437072013-08-30 16:28:46 -0400403 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530404 TPS65217_DEFLS1,
Tom Rini52437072013-08-30 16:28:46 -0400405 TPS65217_LDO_VOLTAGE_OUT_3_3,
406 TPS65217_LDO_MASK))
407 puts("tps65217_reg_write failure\n");
408 } else {
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530409 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
410 TPS65217_DEFLS1,
411 TPS65217_LDO_VOLTAGE_OUT_1_8,
412 TPS65217_LDO_MASK))
413 puts("tps65217_reg_write failure\n");
414 }
Tom Rini52437072013-08-30 16:28:46 -0400415
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530416 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
417 TPS65217_DEFLS2,
418 TPS65217_LDO_VOLTAGE_OUT_3_3,
419 TPS65217_LDO_MASK))
420 puts("tps65217_reg_write failure\n");
421}
Tom Rini52437072013-08-30 16:28:46 -0400422
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530423void scale_vcores_generic(int freq)
424{
425 int sil_rev, mpu_vdd;
Tom Rini52437072013-08-30 16:28:46 -0400426
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530427 /*
428 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
429 * MPU frequencies we support we use a CORE voltage of
430 * 1.10V. For MPU voltage we need to switch based on
431 * the frequency we are running at.
432 */
Jean-Jacques Hiblot52a51512018-12-07 14:50:49 +0100433 if (power_tps65910_init(0))
434 return;
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530435 /*
436 * Depending on MPU clock and PG we will need a different
437 * VDD to drive at that speed.
438 */
439 sil_rev = readl(&cdev->deviceid) >> 28;
440 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
Tom Rini52437072013-08-30 16:28:46 -0400441
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530442 /* Tell the TPS65910 to use i2c */
443 tps65910_set_i2c_control();
Steve Kipisz5adac352013-08-14 10:51:31 -0400444
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530445 /* First update MPU voltage. */
446 if (tps65910_voltage_update(MPU, mpu_vdd))
447 return;
Tom Rini52437072013-08-30 16:28:46 -0400448
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530449 /* Second, update the CORE voltage. */
450 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
451 return;
452
Tom Rini52437072013-08-30 16:28:46 -0400453}
454
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530455void gpi2c_init(void)
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530456{
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530457 /* When needed to be invoked prior to BSS initialization */
458 static bool first_time = true;
459
460 if (first_time) {
461 enable_i2c0_pin_mux();
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530462 first_time = false;
463 }
464}
465
466void scale_vcores(void)
467{
468 int freq;
469
470 gpi2c_init();
471 freq = am335x_get_efuse_mpu_max_freq(cdev);
472
Lokesh Vutlae29609a2017-06-10 13:22:56 +0530473 if (board_is_beaglebonex())
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530474 scale_vcores_bone(freq);
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530475 else
Lokesh Vutla98f9d222017-05-05 12:59:09 +0530476 scale_vcores_generic(freq);
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530477}
478
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530479void set_uart_mux_conf(void)
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000480{
Tom Rini986d7552014-08-01 09:53:24 -0400481#if CONFIG_CONS_INDEX == 1
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000482 enable_uart0_pin_mux();
Tom Rini986d7552014-08-01 09:53:24 -0400483#elif CONFIG_CONS_INDEX == 2
Andrew Bradford65c51ff2012-10-25 08:21:30 -0400484 enable_uart1_pin_mux();
Tom Rini986d7552014-08-01 09:53:24 -0400485#elif CONFIG_CONS_INDEX == 3
Andrew Bradford65c51ff2012-10-25 08:21:30 -0400486 enable_uart2_pin_mux();
Tom Rini986d7552014-08-01 09:53:24 -0400487#elif CONFIG_CONS_INDEX == 4
Andrew Bradford65c51ff2012-10-25 08:21:30 -0400488 enable_uart3_pin_mux();
Tom Rini986d7552014-08-01 09:53:24 -0400489#elif CONFIG_CONS_INDEX == 5
Andrew Bradford65c51ff2012-10-25 08:21:30 -0400490 enable_uart4_pin_mux();
Tom Rini986d7552014-08-01 09:53:24 -0400491#elif CONFIG_CONS_INDEX == 6
Andrew Bradford65c51ff2012-10-25 08:21:30 -0400492 enable_uart5_pin_mux();
Tom Rini986d7552014-08-01 09:53:24 -0400493#endif
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530494}
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000495
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530496void set_mux_conf_regs(void)
497{
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600498 enable_board_pin_mux();
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530499}
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000500
Lokesh Vutla303b2672013-12-10 15:02:21 +0530501const struct ctrl_ioregs ioregs_evmsk = {
502 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
503 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
504 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
505 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
506 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
507};
508
509const struct ctrl_ioregs ioregs_bonelt = {
510 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
511 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
512 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
513 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
514 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
515};
516
517const struct ctrl_ioregs ioregs_evm15 = {
518 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
519 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
520 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
521 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
522 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
523};
524
525const struct ctrl_ioregs ioregs = {
526 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
527 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
528 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
529 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
530 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
531};
532
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530533void sdram_init(void)
534{
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600535 if (board_is_evm_sk()) {
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000536 /*
537 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
538 * This is safe enough to do on older revs.
539 */
540 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
541 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
542 }
543
Lokesh Vutla5837b902016-05-16 11:47:24 +0530544 if (board_is_icev2()) {
545 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
546 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
547 }
548
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600549 if (board_is_evm_sk())
Lokesh Vutla303b2672013-12-10 15:02:21 +0530550 config_ddr(303, &ioregs_evmsk, &ddr3_data,
Matt Porter65991ec2013-03-15 10:07:03 +0000551 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
Jason Kridnerb56b5b32018-03-07 05:40:41 -0500552 else if (board_is_pb() || board_is_bone_lt())
Lokesh Vutla303b2672013-12-10 15:02:21 +0530553 config_ddr(400, &ioregs_bonelt,
Tom Rini385bc752013-03-21 04:30:02 +0000554 &ddr3_beagleblack_data,
555 &ddr3_beagleblack_cmd_ctrl_data,
556 &ddr3_beagleblack_emif_reg_data, 0);
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600557 else if (board_is_evm_15_or_later())
Lokesh Vutla303b2672013-12-10 15:02:21 +0530558 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
Matt Porter65991ec2013-03-15 10:07:03 +0000559 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
Lokesh Vutla5837b902016-05-16 11:47:24 +0530560 else if (board_is_icev2())
561 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
562 &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
563 0);
Jyri Sarha8d2998b2016-12-09 12:29:13 +0200564 else if (board_is_gp_evm())
565 config_ddr(266, &ioregs, &ddr2_data,
566 &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000567 else
Lokesh Vutla303b2672013-12-10 15:02:21 +0530568 config_ddr(266, &ioregs, &ddr2_data,
Matt Porter65991ec2013-03-15 10:07:03 +0000569 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000570}
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530571#endif
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000572
Alex Kiernan20bba2e2018-04-01 09:22:37 +0000573#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
Simon Glasse5cd9a42021-07-10 21:14:26 -0600574 (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)))
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300575static void request_and_set_gpio(int gpio, char *name, int val)
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530576{
577 int ret;
578
579 ret = gpio_request(gpio, name);
580 if (ret < 0) {
581 printf("%s: Unable to request %s\n", __func__, name);
582 return;
583 }
584
585 ret = gpio_direction_output(gpio, 0);
586 if (ret < 0) {
587 printf("%s: Unable to set %s as output\n", __func__, name);
588 goto err_free_gpio;
589 }
590
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300591 gpio_set_value(gpio, val);
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530592
593 return;
594
595err_free_gpio:
596 gpio_free(gpio);
597}
598
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300599#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
600#define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530601
602/**
603 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
604 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
605 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
606 * give 50MHz output for Eth0 and 1.
607 */
608static struct clk_synth cdce913_data = {
609 .id = 0x81,
610 .capacitor = 0x90,
611 .mux = 0x6d,
612 .pdiv2 = 0x2,
613 .pdiv3 = 0x2,
614};
615#endif
616
Sekhar Norif357b112018-08-23 17:11:30 +0530617#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
618 defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
619
620#define MAX_CPSW_SLAVES 2
621
622/* At the moment, we do not want to stop booting for any failures here */
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900623int ft_board_setup(void *fdt, struct bd_info *bd)
Sekhar Norif357b112018-08-23 17:11:30 +0530624{
625 const char *slave_path, *enet_name;
626 int enetnode, slavenode, phynode;
627 struct udevice *ethdev;
628 char alias[16];
629 u32 phy_id[2];
630 int phy_addr;
631 int i, ret;
632
633 /* phy address fixup needed only on beagle bone family */
634 if (!board_is_beaglebonex())
635 goto done;
636
637 for (i = 0; i < MAX_CPSW_SLAVES; i++) {
638 sprintf(alias, "ethernet%d", i);
639
640 slave_path = fdt_get_alias(fdt, alias);
641 if (!slave_path)
642 continue;
643
644 slavenode = fdt_path_offset(fdt, slave_path);
645 if (slavenode < 0)
646 continue;
647
648 enetnode = fdt_parent_offset(fdt, slavenode);
649 enet_name = fdt_get_name(fdt, enetnode, NULL);
650
651 ethdev = eth_get_dev_by_name(enet_name);
652 if (!ethdev)
653 continue;
654
655 phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
656
657 /* check for phy_id as well as phy-handle properties */
658 ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
659 phy_id, 2);
660 if (ret == 2) {
661 if (phy_id[1] != phy_addr) {
662 printf("fixing up phy_id for %s, old: %d, new: %d\n",
663 alias, phy_id[1], phy_addr);
664
665 phy_id[0] = cpu_to_fdt32(phy_id[0]);
666 phy_id[1] = cpu_to_fdt32(phy_addr);
667 do_fixup_by_path(fdt, slave_path, "phy_id",
668 phy_id, sizeof(phy_id), 0);
669 }
670 } else {
671 phynode = fdtdec_lookup_phandle(fdt, slavenode,
672 "phy-handle");
673 if (phynode < 0)
674 continue;
675
676 ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
677 if (ret < 0)
678 continue;
679
680 if (ret != phy_addr) {
681 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
682 alias, ret, phy_addr);
683
684 fdt_setprop_u32(fdt, phynode, "reg",
685 cpu_to_fdt32(phy_addr));
686 }
687 }
688 }
689
690done:
691 return 0;
692}
693#endif
694
Amjad Ouled-Ameur4d797722021-10-29 16:08:17 +0200695static bool __maybe_unused prueth_is_mii = true;
696
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000697/*
698 * Basic board specific setup. Pinmux has been handled already.
699 */
700int board_init(void)
701{
Tom Rini303bfe82013-10-01 12:32:04 -0400702#if defined(CONFIG_HW_WATCHDOG)
703 hw_watchdog_init();
704#endif
705
Tom Rinibb4dd962022-11-16 13:10:37 -0500706 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
Miquel Raynald0935362019-10-03 19:50:03 +0200707#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
Ilya Yanok3d9725e2012-11-06 13:06:31 +0000708 gpmc_init();
Steve Kipiszbe9b6f82013-07-18 15:13:03 -0400709#endif
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530710
Alex Kiernan20bba2e2018-04-01 09:22:37 +0000711#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
Simon Glasse5cd9a42021-07-10 21:14:26 -0600712 (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)))
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530713 if (board_is_icev2()) {
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300714 int rv;
715 u32 reg;
Amjad Ouled-Ameur4d797722021-10-29 16:08:17 +0200716 bool eth0_is_mii = true;
717 bool eth1_is_mii = true;
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300718
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530719 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300720 /* Make J19 status available on GPIO1_26 */
721 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
722
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530723 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300724 /*
725 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
726 * jumpers near the port. Read the jumper value and set
727 * the pinmux, external mux and PHY clock accordingly.
728 * As jumper line is overridden by PHY RX_DV pin immediately
729 * after bootstrap (power-up/reset), we need to sample
730 * it during PHY reset using GPIO rising edge detection.
731 */
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530732 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300733 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
734 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
735 writel(reg, GPIO0_RISINGDETECT);
736 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
737 writel(reg, GPIO1_RISINGDETECT);
738 /* Reset PHYs to capture the Jumper setting */
739 gpio_set_value(GPIO_PHY_RESET, 0);
740 udelay(2); /* PHY datasheet states 1uS min. */
741 gpio_set_value(GPIO_PHY_RESET, 1);
742
743 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
744 if (reg) {
745 writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
746 /* RMII mode */
747 printf("ETH0, CPSW\n");
Amjad Ouled-Ameur4d797722021-10-29 16:08:17 +0200748 eth0_is_mii = false;
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300749 } else {
750 /* MII mode */
751 printf("ETH0, PRU\n");
752 cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
753 }
754
755 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
756 if (reg) {
757 writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
758 /* RMII mode */
759 printf("ETH1, CPSW\n");
760 gpio_set_value(GPIO_MUX_MII_CTRL, 1);
Amjad Ouled-Ameur4d797722021-10-29 16:08:17 +0200761 eth1_is_mii = false;
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300762 } else {
763 /* MII mode */
764 printf("ETH1, PRU\n");
765 cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
766 }
767
Amjad Ouled-Ameur4d797722021-10-29 16:08:17 +0200768 if (eth0_is_mii != eth1_is_mii) {
769 printf("Unsupported Ethernet port configuration\n");
770 printf("Both ports must be set as RMII or MII\n");
771 hang();
772 }
773
774 prueth_is_mii = eth0_is_mii;
775
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300776 /* disable rising edge IRQs */
777 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
778 writel(reg, GPIO0_RISINGDETECT);
779 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
780 writel(reg, GPIO1_RISINGDETECT);
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530781
782 rv = setup_clock_synthesizer(&cdce913_data);
783 if (rv) {
784 printf("Clock synthesizer setup failed %d\n", rv);
785 return rv;
786 }
Roger Quadrosbcb4ee82016-08-24 15:35:50 +0300787
788 /* reset PHYs */
789 gpio_set_value(GPIO_PHY_RESET, 0);
790 udelay(2); /* PHY datasheet states 1uS min. */
791 gpio_set_value(GPIO_PHY_RESET, 1);
Lokesh Vutla0d144f52016-05-16 11:47:26 +0530792 }
793#endif
794
Peter Korsgaard85ec2db2012-10-18 01:21:09 +0000795 return 0;
796}
797
Tom Rini40271852012-10-24 07:28:17 +0000798#ifdef CONFIG_BOARD_LATE_INIT
799int board_late_init(void)
800{
Tero Kristo67f79e72019-09-27 19:14:29 +0300801 struct udevice *dev;
Roger Quadros7c9d3782016-08-24 15:35:51 +0300802#if !defined(CONFIG_SPL_BUILD)
803 uint8_t mac_addr[6];
804 uint32_t mac_hi, mac_lo;
805#endif
806
Tom Rini40271852012-10-24 07:28:17 +0000807#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600808 char *name = NULL;
Tom Rini4021fd92013-07-18 15:13:01 -0400809
robertcnelson@gmail.comc5d7d222017-03-30 14:29:52 -0500810 if (board_is_bone_lt()) {
811 /* BeagleBoard.org BeagleBone Black Wireless: */
812 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
813 name = "BBBW";
814 }
robertcnelson@gmail.comb55cd7a2017-03-30 14:29:53 -0500815 /* SeeedStudio BeagleBone Green Wireless */
816 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
817 name = "BBGW";
818 }
robertcnelson@gmail.com89ef1d62017-03-30 14:29:54 -0500819 /* BeagleBoard.org BeagleBone Blue */
820 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
821 name = "BBBL";
822 }
robertcnelson@gmail.comc5d7d222017-03-30 14:29:52 -0500823 }
824
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600825 if (board_is_bbg1())
826 name = "BBG1";
Paul Barker10a59442022-04-11 15:42:00 +0000827 if (board_is_bben()) {
828 char subtype_id = board_ti_get_config()[1];
829
Paul Barker726ae6e2022-04-11 15:42:01 +0000830 switch (subtype_id) {
831 case 'L':
Paul Barker10a59442022-04-11 15:42:00 +0000832 name = "BBELITE";
Paul Barker726ae6e2022-04-11 15:42:01 +0000833 break;
834 case 'I':
835 name = "BBE_EX_WIFI";
836 break;
837 default:
Paul Barker10a59442022-04-11 15:42:00 +0000838 name = "BBEN";
Paul Barker726ae6e2022-04-11 15:42:01 +0000839 }
Paul Barker10a59442022-04-11 15:42:00 +0000840 }
Nishanth Menon2afa70d2016-02-24 12:30:55 -0600841 set_board_info_env(name);
Lokesh Vutla1eb0f542016-11-29 11:58:03 +0530842
843 /*
844 * Default FIT boot on HS devices. Non FIT images are not allowed
845 * on HS devices.
846 */
847 if (get_device_type() == HS_DEVICE)
Simon Glass6a38e412017-08-03 12:22:09 -0600848 env_set("boot_fit", "1");
Tom Rini40271852012-10-24 07:28:17 +0000849#endif
850
Roger Quadros7c9d3782016-08-24 15:35:51 +0300851#if !defined(CONFIG_SPL_BUILD)
852 /* try reading mac address from efuse */
853 mac_lo = readl(&cdev->macid0l);
854 mac_hi = readl(&cdev->macid0h);
855 mac_addr[0] = mac_hi & 0xFF;
856 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
857 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
858 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
859 mac_addr[4] = mac_lo & 0xFF;
860 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
861
Simon Glass64b723f2017-08-03 12:22:12 -0600862 if (!env_get("ethaddr")) {
Roger Quadros7c9d3782016-08-24 15:35:51 +0300863 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
864
865 if (is_valid_ethaddr(mac_addr))
Simon Glass8551d552017-08-03 12:22:11 -0600866 eth_env_set_enetaddr("ethaddr", mac_addr);
Roger Quadros7c9d3782016-08-24 15:35:51 +0300867 }
868
869 mac_lo = readl(&cdev->macid1l);
870 mac_hi = readl(&cdev->macid1h);
871 mac_addr[0] = mac_hi & 0xFF;
872 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
873 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
874 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
875 mac_addr[4] = mac_lo & 0xFF;
876 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
877
Simon Glass64b723f2017-08-03 12:22:12 -0600878 if (!env_get("eth1addr")) {
Roger Quadros7c9d3782016-08-24 15:35:51 +0300879 if (is_valid_ethaddr(mac_addr))
Simon Glass8551d552017-08-03 12:22:11 -0600880 eth_env_set_enetaddr("eth1addr", mac_addr);
Roger Quadros7c9d3782016-08-24 15:35:51 +0300881 }
Amjad Ouled-Ameur4d797722021-10-29 16:08:17 +0200882
883 env_set("ice_mii", prueth_is_mii ? "mii" : "rmii");
Roger Quadros7c9d3782016-08-24 15:35:51 +0300884#endif
885
Sam Protsenkoa31ca622018-02-28 00:26:15 +0200886 if (!env_get("serial#")) {
887 char *board_serial = env_get("board_serial");
888 char *ethaddr = env_get("ethaddr");
889
890 if (!board_serial || !strncmp(board_serial, "unknown", 7))
891 env_set("serial#", ethaddr);
892 else
893 env_set("serial#", board_serial);
894 }
895
Tero Kristo67f79e72019-09-27 19:14:29 +0300896 /* Just probe the potentially supported cdce913 device */
Dario Binacchic2de9d42020-12-30 00:16:32 +0100897 uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
Tero Kristo67f79e72019-09-27 19:14:29 +0300898
Tom Rini40271852012-10-24 07:28:17 +0000899 return 0;
900}
901#endif
902
Simon Glass71fa5b42020-12-03 16:55:18 -0700903/* CPSW plat */
Corentin LABBE58cbef52022-06-14 08:44:07 +0000904#if CONFIG_IS_ENABLED(NET) && !CONFIG_IS_ENABLED(OF_CONTROL)
Faiz Abbas27866262019-03-18 13:54:37 +0530905struct cpsw_slave_data slave_data[] = {
906 {
907 .slave_reg_ofs = CPSW_SLAVE0_OFFSET,
908 .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
909 .phy_addr = 0,
910 },
911 {
912 .slave_reg_ofs = CPSW_SLAVE1_OFFSET,
913 .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
914 .phy_addr = 1,
915 },
916};
917
918struct cpsw_platform_data am335_eth_data = {
919 .cpsw_base = CPSW_BASE,
920 .version = CPSW_CTRL_VERSION_2,
921 .bd_ram_ofs = CPSW_BD_OFFSET,
922 .ale_reg_ofs = CPSW_ALE_OFFSET,
923 .cpdma_reg_ofs = CPSW_CPDMA_OFFSET,
924 .mdio_div = CPSW_MDIO_DIV,
925 .host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
926 .channels = 8,
927 .slaves = 2,
928 .slave_data = slave_data,
929 .ale_entries = 1024,
Faiz Abbas27866262019-03-18 13:54:37 +0530930 .mac_control = 0x20,
931 .active_slave = 0,
932 .mdio_base = 0x4a101000,
933 .gmii_sel = 0x44e10650,
934 .phy_sel_compat = "ti,am3352-cpsw-phy-sel",
935 .syscon_addr = 0x44e10630,
936 .macid_sel_compat = "cpsw,am33xx",
937};
938
939struct eth_pdata cpsw_pdata = {
940 .iobase = 0x4a100000,
941 .phy_interface = 0,
942 .priv_pdata = &am335_eth_data,
943};
944
Simon Glass1d8364a2020-12-28 20:34:54 -0700945U_BOOT_DRVINFO(am335x_eth) = {
Faiz Abbas27866262019-03-18 13:54:37 +0530946 .name = "eth_cpsw",
Simon Glass71fa5b42020-12-03 16:55:18 -0700947 .plat = &cpsw_pdata,
Faiz Abbas27866262019-03-18 13:54:37 +0530948};
949#endif
950
Lokesh Vutla89b9f302016-05-16 11:24:24 +0530951#ifdef CONFIG_SPL_LOAD_FIT
952int board_fit_config_name_match(const char *name)
953{
954 if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
955 return 0;
956 else if (board_is_bone() && !strcmp(name, "am335x-bone"))
957 return 0;
958 else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
959 return 0;
Jason Kridnerb56b5b32018-03-07 05:40:41 -0500960 else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
961 return 0;
Lokesh Vutla5a954ba2016-05-16 11:24:28 +0530962 else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
963 return 0;
Lokesh Vutla1edfcaf2016-05-16 11:24:29 +0530964 else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
965 return 0;
Lokesh Vutla7ecf1962016-05-16 11:47:28 +0530966 else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
967 return 0;
Paul Barker1977f3e2022-07-08 10:25:46 +0100968 else if (board_is_bben()) {
969 char subtype_id = board_ti_get_config()[1];
970
971 if (subtype_id == 'L') {
972 if (!strcmp(name, "am335x-sancloud-bbe-lite"))
973 return 0;
974 } else if (subtype_id == 'I') {
975 if (!strcmp(name, "am335x-sancloud-bbe-extended-wifi"))
976 return 0;
977 } else if (!strcmp(name, "am335x-sancloud-bbe")) {
978 return 0;
979 }
980 }
981 return -1;
Lokesh Vutla89b9f302016-05-16 11:24:24 +0530982}
983#endif
Andrew F. Davisbd249152016-08-30 14:06:24 -0500984
Lokesh Vutla2fe7c792017-04-26 13:37:08 +0530985#if !CONFIG_IS_ENABLED(OF_CONTROL)
Simon Glassb75b15b2020-12-03 16:55:23 -0700986static const struct omap_hsmmc_plat am335x_mmc0_plat = {
Lokesh Vutla2fe7c792017-04-26 13:37:08 +0530987 .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
988 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
989 .cfg.f_min = 400000,
990 .cfg.f_max = 52000000,
991 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
992 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
993};
994
Simon Glass1d8364a2020-12-28 20:34:54 -0700995U_BOOT_DRVINFO(am335x_mmc0) = {
Lokesh Vutla2fe7c792017-04-26 13:37:08 +0530996 .name = "omap_hsmmc",
Simon Glassb75b15b2020-12-03 16:55:23 -0700997 .plat = &am335x_mmc0_plat,
Lokesh Vutla2fe7c792017-04-26 13:37:08 +0530998};
999
Simon Glassb75b15b2020-12-03 16:55:23 -07001000static const struct omap_hsmmc_plat am335x_mmc1_plat = {
Lokesh Vutla2fe7c792017-04-26 13:37:08 +05301001 .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
1002 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
1003 .cfg.f_min = 400000,
1004 .cfg.f_max = 52000000,
1005 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
1006 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
1007};
1008
Simon Glass1d8364a2020-12-28 20:34:54 -07001009U_BOOT_DRVINFO(am335x_mmc1) = {
Lokesh Vutla2fe7c792017-04-26 13:37:08 +05301010 .name = "omap_hsmmc",
Simon Glassb75b15b2020-12-03 16:55:23 -07001011 .plat = &am335x_mmc1_plat,
Lokesh Vutla2fe7c792017-04-26 13:37:08 +05301012};
1013#endif