blob: 7abc41269330d4e8cc4287fd0e0ca16c6ead5727 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Feng Li39e112d2016-11-03 14:15:17 +08002/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
Gaurav Jain476c6392022-03-24 11:50:35 +05304 * Copyright 2021 NXP
Feng Li39e112d2016-11-03 14:15:17 +08005 */
6
Tom Riniaf026762024-04-30 20:41:48 -06007#include <config.h>
Simon Glass85d65312019-12-28 10:44:58 -07008#include <clock_legacy.h>
Simon Glass3bbe70c2019-12-28 10:44:54 -07009#include <fdt_support.h>
Simon Glassa7b51302019-11-14 12:57:46 -070010#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060011#include <net.h>
Feng Li39e112d2016-11-03 14:15:17 +080012#include <asm/arch/immap_ls102xa.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/fsl_serdes.h>
15#include <asm/arch/ls102xa_stream_id.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060016#include <asm/global_data.h>
Simon Glassdbd79542020-05-10 11:40:11 -060017#include <linux/delay.h>
Feng Li39e112d2016-11-03 14:15:17 +080018
19#include <asm/arch/ls102xa_devdis.h>
20#include <asm/arch/ls102xa_soc.h>
Shiji Yangbb112342023-08-03 09:47:16 +080021#include <asm/sections.h>
Feng Li39e112d2016-11-03 14:15:17 +080022#include <fsl_csu.h>
Feng Li39e112d2016-11-03 14:15:17 +080023#include <fsl_immap.h>
24#include <netdev.h>
25#include <fsl_mdio.h>
26#include <tsec.h>
27#include <spl.h>
28
29#include <fsl_validate.h>
30#include "../common/sleep.h"
31
32DECLARE_GLOBAL_DATA_PTR;
33
34#define DDR_SIZE 0x40000000
35
36
37int checkboard(void)
38{
39 puts("Board: LS1021AIOT\n");
40
41#ifndef CONFIG_QSPI_BOOT
Tom Rini376b88a2022-10-28 20:27:13 -040042 struct ccsr_gur *dcfg = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR;
Feng Li39e112d2016-11-03 14:15:17 +080043 u32 cpldrev;
44
45 cpldrev = in_be32(&dcfg->gpporcr1);
46
47 printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
48 0xf));
49#endif
50 return 0;
51}
52
53void ddrmc_init(void)
54{
Tom Rini376b88a2022-10-28 20:27:13 -040055 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR;
Feng Li39e112d2016-11-03 14:15:17 +080056 u32 temp_sdram_cfg, tmp;
57
58 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
59
60 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
61 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
62
63 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
64 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
65 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
66 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
67 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
68 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
69
70 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
71 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
72
73 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
74 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
75
76 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
77
78 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
79
80 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
81 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
82
83 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
84
85 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
86 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
87
88 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
89
90 /* DDR erratum A-009942 */
91 tmp = in_be32(&ddr->debug[28]);
92 out_be32(&ddr->debug[28], tmp | 0x0070006f);
93
94 udelay(500);
95
96 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
97
98 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
99}
100
101int dram_init(void)
102{
103#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
104 ddrmc_init();
105#endif
106
Alison Wangd6be97b2019-03-06 14:49:14 +0800107 erratum_a008850_post();
108
Feng Li39e112d2016-11-03 14:15:17 +0800109 gd->ram_size = DDR_SIZE;
110 return 0;
111}
112
Feng Li39e112d2016-11-03 14:15:17 +0800113int board_early_init_f(void)
114{
Tom Rini376b88a2022-10-28 20:27:13 -0400115 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
Feng Li39e112d2016-11-03 14:15:17 +0800116
117#ifdef CONFIG_TSEC_ENET
118 /* clear BD & FR bits for BE BD's and frame data */
119 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
120 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
121
122#endif
123
124 arch_soc_init();
125
126 return 0;
127}
128
129#ifdef CONFIG_SPL_BUILD
130void board_init_f(ulong dummy)
131{
132 /* Clear the BSS */
133 memset(__bss_start, 0, __bss_end - __bss_start);
134
135 get_clocks();
136
137 preloader_console_init();
138
139 dram_init();
140
141 /* Allow OCRAM access permission as R/W */
142
143#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
144 enable_layerscape_ns_access();
145#endif
146
147 board_init_r(NULL, 0);
148}
149#endif
150
151int board_init(void)
152{
153#ifndef CONFIG_SYS_FSL_NO_SERDES
154 fsl_serdes_init();
155#endif
156
157 ls102xa_smmu_stream_id_init();
158
Feng Li39e112d2016-11-03 14:15:17 +0800159 return 0;
160}
161
162#ifdef CONFIG_BOARD_LATE_INIT
163int board_late_init(void)
164{
Feng Li39e112d2016-11-03 14:15:17 +0800165 return 0;
166}
167#endif
168
169#if defined(CONFIG_MISC_INIT_R)
170int misc_init_r(void)
171{
172#ifdef CONFIG_FSL_DEVICE_DISABLE
173 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
174
175#endif
Gaurav Jain476c6392022-03-24 11:50:35 +0530176 return 0;
Feng Li39e112d2016-11-03 14:15:17 +0800177}
178#endif
179
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900180int ft_board_setup(void *blob, struct bd_info *bd)
Feng Li39e112d2016-11-03 14:15:17 +0800181{
182 ft_cpu_setup(blob, bd);
183
184#ifdef CONFIG_PCI
185 ft_pci_setup(blob, bd);
186#endif
187
188 return 0;
189}
190
191void flash_write16(u16 val, void *addr)
192{
193 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
194
195 __raw_writew(shftval, addr);
196}
197
198u16 flash_read16(void *addr)
199{
200 u16 val = __raw_readw(addr);
201
202 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
203}