blob: eab3398c4aec84c470fa40ec6574678a54288936 [file] [log] [blame]
Sjoerd Simonsf93564c2019-02-25 15:33:00 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * mux.c
4 *
Nishanth Menoneaa39c62023-11-01 15:56:03 -05005 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
Sjoerd Simonsf93564c2019-02-25 15:33:00 +00006 * Copyright (C) 2018 Robert Bosch Power Tools GmbH
7 */
8
Sjoerd Simonsf93564c2019-02-25 15:33:00 +00009#include <i2c.h>
10#include <asm/arch/hardware.h>
11#include <asm/arch/mux.h>
12#include <asm/arch/sys_proto.h>
13#include <asm/io.h>
14#include "board.h"
15
16static struct module_pin_mux uart0_pin_mux[] = {
17 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
19 {-1},
20};
21
22static struct module_pin_mux i2c0_pin_mux[] = {
23 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
24 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
25 {-1},
26};
27
Moses Christopher5d489f82019-09-17 14:25:37 +000028static struct module_pin_mux guardian_interfaces_pin_mux[] = {
29 {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLDOWN_EN)},
Gireesh Hiremath6b755fa2021-06-11 16:13:47 +000030 {OFFSET(mii1_txen), (MODE(7) | PULLDOWN_EN)},
Moses Christopher5d489f82019-09-17 14:25:37 +000031 {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)},
Gireesh Hiremath6b755fa2021-06-11 16:13:47 +000032 {OFFSET(mdio_clk), (MODE(7) | PULLUP_EN)},
Moses Christopher5d489f82019-09-17 14:25:37 +000033 {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
34 {OFFSET(uart1_txd), (MODE(7) | PULLUDDIS)},
35 {OFFSET(mii1_crs), (MODE(7) | PULLDOWN_EN)},
36 {OFFSET(rmii1_refclk), (MODE(7) | PULLDOWN_EN)},
37 {OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},
38 {OFFSET(mii1_rxdv), (MODE(7) | PULLDOWN_EN)},
Sjoerd Simonsf93564c2019-02-25 15:33:00 +000039 {-1},
40};
41
Miquel Raynald0935362019-10-03 19:50:03 +020042#ifdef CONFIG_MTD_RAW_NAND
Sjoerd Simonsf93564c2019-02-25 15:33:00 +000043static struct module_pin_mux nand_pin_mux[] = {
44 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)},
45 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)},
46 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)},
47 {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)},
48 {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)},
49 {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)},
50 {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)},
51 {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)},
52#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
53 {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)},
54 {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)},
55 {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)},
56 {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)},
57 {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)},
58 {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)},
59 {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)},
60 {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)},
61#endif
62 {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)},
63 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)},
64 {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
65 {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)},
66 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)},
67 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},
68 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},
69 {-1},
70};
71#endif
72
73void enable_uart0_pin_mux(void)
74{
75 configure_module_pin_mux(uart0_pin_mux);
76}
77
78void enable_i2c0_pin_mux(void)
79{
80 configure_module_pin_mux(i2c0_pin_mux);
81}
82
83void enable_board_pin_mux(void)
84{
Miquel Raynald0935362019-10-03 19:50:03 +020085#ifdef CONFIG_MTD_RAW_NAND
Sjoerd Simonsf93564c2019-02-25 15:33:00 +000086 configure_module_pin_mux(nand_pin_mux);
87#endif
Moses Christopher5d489f82019-09-17 14:25:37 +000088 configure_module_pin_mux(guardian_interfaces_pin_mux);
Sjoerd Simonsf93564c2019-02-25 15:33:00 +000089}