blob: 8ae4798f125ce8e4aea077111d39d9a6444e062a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass17f1c402014-11-14 18:18:32 -07002/*
3 * Copyright (C) 2014 Google, Inc
Simon Glass17f1c402014-11-14 18:18:32 -07004 */
Simon Glasse0e7b362015-03-05 12:25:33 -07005#include <dm.h>
Simon Glass17f1c402014-11-14 18:18:32 -07006#include <errno.h>
7#include <fdtdec.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
Simon Glass17f1c402014-11-14 18:18:32 -07009#include <malloc.h>
Simon Glass32761632016-01-18 20:19:21 -070010#include <pch.h>
Simon Glassa75abeb2016-01-17 16:11:59 -070011#include <asm/cpu.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Simon Glassab39d332016-03-11 22:06:56 -070013#include <asm/intel_regs.h>
Simon Glass6c9e1d82016-01-17 16:11:53 -070014#include <asm/io.h>
Simon Glass17f1c402014-11-14 18:18:32 -070015#include <asm/lapic.h>
Simon Glass63e08a22016-03-11 22:06:57 -070016#include <asm/lpc_common.h>
Simon Glass17f1c402014-11-14 18:18:32 -070017#include <asm/pci.h>
Simon Glass17f1c402014-11-14 18:18:32 -070018#include <asm/arch/model_206ax.h>
19#include <asm/arch/pch.h>
20#include <asm/arch/sandybridge.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060021#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060022#include <linux/delay.h>
Simon Glass17f1c402014-11-14 18:18:32 -070023
Simon Glassd87b0922017-01-16 07:03:37 -070024DECLARE_GLOBAL_DATA_PTR;
25
Simon Glass1a9360d2019-02-16 20:24:52 -070026#define GPIO_BASE 0x48
27#define BIOS_CTRL 0xdc
28
29#define RCBA_AUDIO_CONFIG 0x2030
30#define RCBA_AUDIO_CONFIG_HDA BIT(31)
31#define RCBA_AUDIO_CONFIG_MASK 0xfe
Simon Glass32761632016-01-18 20:19:21 -070032
Simon Glass6c9e1d82016-01-17 16:11:53 -070033static int pch_revision_id = -1;
34static int pch_type = -1;
35
36/**
37 * pch_silicon_revision() - Read silicon revision ID from the PCH
38 *
39 * @dev: PCH device
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010040 * Return: silicon revision ID
Simon Glass6c9e1d82016-01-17 16:11:53 -070041 */
42static int pch_silicon_revision(struct udevice *dev)
43{
44 u8 val;
45
46 if (pch_revision_id < 0) {
47 dm_pci_read_config8(dev, PCI_REVISION_ID, &val);
48 pch_revision_id = val;
49 }
50
51 return pch_revision_id;
52}
53
54int pch_silicon_type(struct udevice *dev)
55{
56 u8 val;
57
58 if (pch_type < 0) {
59 dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val);
60 pch_type = val;
61 }
62
63 return pch_type;
64}
65
66/**
67 * pch_silicon_supported() - Check if a certain revision is supported
68 *
69 * @dev: PCH device
70 * @type: PCH type
71 * @rev: Minimum required resion
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010072 * Return: 0 if not supported, 1 if supported
Simon Glass6c9e1d82016-01-17 16:11:53 -070073 */
74static int pch_silicon_supported(struct udevice *dev, int type, int rev)
75{
76 int cur_type = pch_silicon_type(dev);
77 int cur_rev = pch_silicon_revision(dev);
78
79 switch (type) {
80 case PCH_TYPE_CPT:
81 /* CougarPoint minimum revision */
82 if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
83 return 1;
84 /* PantherPoint any revision */
85 if (cur_type == PCH_TYPE_PPT)
86 return 1;
87 break;
88
89 case PCH_TYPE_PPT:
90 /* PantherPoint minimum revision */
91 if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
92 return 1;
93 break;
94 }
95
96 return 0;
97}
98
99#define IOBP_RETRY 1000
100static inline int iobp_poll(void)
101{
102 unsigned try = IOBP_RETRY;
103 u32 data;
104
105 while (try--) {
106 data = readl(RCB_REG(IOBPS));
107 if ((data & 1) == 0)
108 return 1;
109 udelay(10);
110 }
111
112 printf("IOBP timeout\n");
113 return 0;
114}
115
116void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
117 u32 orvalue)
118{
119 u32 data;
120
121 /* Set the address */
122 writel(address, RCB_REG(IOBPIRI));
123
124 /* READ OPCODE */
125 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
126 writel(IOBPS_RW_BX, RCB_REG(IOBPS));
127 else
128 writel(IOBPS_READ_AX, RCB_REG(IOBPS));
129 if (!iobp_poll())
130 return;
131
132 /* Read IOBP data */
133 data = readl(RCB_REG(IOBPD));
134 if (!iobp_poll())
135 return;
136
137 /* Check for successful transaction */
138 if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) {
139 printf("IOBP read 0x%08x failed\n", address);
140 return;
141 }
142
143 /* Update the data */
144 data &= andvalue;
145 data |= orvalue;
146
147 /* WRITE OPCODE */
148 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
149 writel(IOBPS_RW_BX, RCB_REG(IOBPS));
150 else
151 writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
152 if (!iobp_poll())
153 return;
154
155 /* Write IOBP data */
156 writel(data, RCB_REG(IOBPD));
157 if (!iobp_poll())
158 return;
159}
160
Simon Glasse0e7b362015-03-05 12:25:33 -0700161static int bd82x6x_probe(struct udevice *dev)
Simon Glass17f1c402014-11-14 18:18:32 -0700162{
Simon Glass833eecd2023-05-04 16:50:49 -0600163 /* make sure the LPC is inited since it provides the gpio base */
164 uclass_first_device(UCLASS_LPC, &dev);
Simon Glass044f1a02016-01-17 16:11:10 -0700165
Simon Glass833eecd2023-05-04 16:50:49 -0600166 if (!IS_ENABLED(CONFIG_HAVE_FSP)) {
167 if (!(gd->flags & GD_FLG_RELOC))
168 return 0;
169
170 /* Cause the SATA device to do its init */
171 uclass_first_device(UCLASS_AHCI, &dev);
172 }
Simon Glass39f3f8c2016-01-17 16:11:37 -0700173
Simon Glass17f1c402014-11-14 18:18:32 -0700174 return 0;
175}
176
Bin Meng06d66af2016-02-01 01:40:42 -0800177static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
Simon Glass32761632016-01-18 20:19:21 -0700178{
179 u32 rcba;
180
181 dm_pci_read_config32(dev, PCH_RCBA, &rcba);
182 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
183 rcba = rcba & 0xffffc000;
184 *sbasep = rcba + 0x3800;
185
186 return 0;
187}
188
Simon Glass32761632016-01-18 20:19:21 -0700189static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
190{
Simon Glass63e08a22016-03-11 22:06:57 -0700191 return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
Simon Glass32761632016-01-18 20:19:21 -0700192}
193
Bin Mengfd2afdf2016-02-01 01:40:44 -0800194static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep)
195{
196 u32 base;
197
198 /*
199 * GPIO_BASE moved to its current offset with ICH6, but prior to
200 * that it was unused (or undocumented). Check that it looks
201 * okay: not all ones or zeros.
202 *
203 * Note we don't need check bit0 here, because the Tunnel Creek
204 * GPIO base address register bit0 is reserved (read returns 0),
205 * while on the Ivybridge the bit0 is used to indicate it is an
206 * I/O space.
207 */
208 dm_pci_read_config32(dev, GPIO_BASE, &base);
209 if (base == 0x00000000 || base == 0xffffffff) {
210 debug("%s: unexpected BASE value\n", __func__);
211 return -ENODEV;
212 }
213
214 /*
215 * Okay, I guess we're looking at the right device. The actual
216 * GPIO registers are in the PCI device's I/O space, starting
217 * at the offset that we just read. Bit 0 indicates that it's
218 * an I/O address, not a memory address, so mask that off.
219 */
220 *gbasep = base & 1 ? base & ~3 : base & ~15;
221
222 return 0;
223}
224
Simon Glass1a9360d2019-02-16 20:24:52 -0700225static int bd82x6x_ioctl(struct udevice *dev, enum pch_req_t req, void *data,
226 int size)
227{
228 u32 rcba, val;
229
230 switch (req) {
231 case PCH_REQ_HDA_CONFIG:
232 dm_pci_read_config32(dev, PCH_RCBA, &rcba);
233 val = readl(rcba + RCBA_AUDIO_CONFIG);
234 if (!(val & RCBA_AUDIO_CONFIG_HDA))
235 return -ENOENT;
236
237 return val & RCBA_AUDIO_CONFIG_MASK;
Simon Glass027f8372019-04-25 21:59:02 -0600238 case PCH_REQ_PMBASE_INFO: {
239 struct pch_pmbase_info *pm = data;
240 int ret;
241
242 /* Find the base address of the powermanagement registers */
243 ret = dm_pci_read_config16(dev, 0x40, &pm->base);
244 if (ret)
245 return ret;
246 pm->base &= 0xfffe;
247 pm->gpio0_en_ofs = GPE0_EN;
248 pm->pm1_sts_ofs = PM1_STS;
249 pm->pm1_cnt_ofs = PM1_CNT;
250
251 return 0;
252 }
Simon Glass1a9360d2019-02-16 20:24:52 -0700253 default:
254 return -ENOSYS;
255 }
256}
257
Simon Glass32761632016-01-18 20:19:21 -0700258static const struct pch_ops bd82x6x_pch_ops = {
Bin Meng06d66af2016-02-01 01:40:42 -0800259 .get_spi_base = bd82x6x_pch_get_spi_base,
Simon Glass32761632016-01-18 20:19:21 -0700260 .set_spi_protect = bd82x6x_set_spi_protect,
Bin Mengfd2afdf2016-02-01 01:40:44 -0800261 .get_gpio_base = bd82x6x_get_gpio_base,
Simon Glass1a9360d2019-02-16 20:24:52 -0700262 .ioctl = bd82x6x_ioctl,
Simon Glass32761632016-01-18 20:19:21 -0700263};
264
Simon Glasse0e7b362015-03-05 12:25:33 -0700265static const struct udevice_id bd82x6x_ids[] = {
266 { .compatible = "intel,bd82x6x" },
267 { }
268};
269
270U_BOOT_DRIVER(bd82x6x_drv) = {
271 .name = "bd82x6x",
272 .id = UCLASS_PCH,
273 .of_match = bd82x6x_ids,
274 .probe = bd82x6x_probe,
Simon Glass32761632016-01-18 20:19:21 -0700275 .ops = &bd82x6x_pch_ops,
Simon Glasse0e7b362015-03-05 12:25:33 -0700276};