Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2000-2002 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 5 | * |
| 6 | * (C) Copyright 2002 (440 port) |
| 7 | * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com |
| 8 | * |
| 9 | * (C) Copyright 2003 Motorola Inc. (MPC85xx port) |
| 10 | * Xianghua Xiao (X.Xiao@motorola.com) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 11 | */ |
| 12 | |
Tom Rini | b01c75d | 2024-04-27 08:10:57 -0600 | [diff] [blame] | 13 | #include <asm/ppc.h> |
Simon Glass | 9b61c7c | 2019-11-14 12:57:41 -0700 | [diff] [blame] | 14 | #include <irq_func.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 15 | #include <log.h> |
Simon Glass | a9dc068 | 2019-12-28 10:44:59 -0700 | [diff] [blame] | 16 | #include <time.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 17 | #include <watchdog.h> |
| 18 | #include <command.h> |
| 19 | #include <asm/processor.h> |
Timur Tabi | c5abd7a | 2009-08-20 17:41:11 -0500 | [diff] [blame] | 20 | #include <asm/io.h> |
John Schmoller | a9cecd5 | 2011-03-10 16:09:26 -0600 | [diff] [blame] | 21 | #ifdef CONFIG_POST |
| 22 | #include <post.h> |
| 23 | #endif |
Simon Glass | 6b9f010 | 2020-05-10 11:40:06 -0600 | [diff] [blame] | 24 | #include <asm/ptrace.h> |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 25 | |
Tom Rini | ce10398 | 2017-08-13 22:44:37 -0400 | [diff] [blame] | 26 | void interrupt_init_cpu(unsigned *decrementer_count) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 27 | { |
Tom Rini | d5c3bf2 | 2022-10-28 20:27:12 -0400 | [diff] [blame] | 28 | ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR; |
wdenk | f3da7cc | 2005-05-13 22:49:36 +0000 | [diff] [blame] | 29 | |
John Schmoller | a9cecd5 | 2011-03-10 16:09:26 -0600 | [diff] [blame] | 30 | #ifdef CONFIG_POST |
| 31 | /* |
| 32 | * The POST word is stored in the PIC's TFRR register which gets |
| 33 | * cleared when the PIC is reset. Save it off so we can restore it |
| 34 | * later. |
| 35 | */ |
| 36 | ulong post_word = post_word_load(); |
| 37 | #endif |
| 38 | |
Timur Tabi | c5abd7a | 2009-08-20 17:41:11 -0500 | [diff] [blame] | 39 | out_be32(&pic->gcr, MPC85xx_PICGCR_RST); |
| 40 | while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) |
Kumar Gala | 4f6280e | 2008-08-19 14:46:36 -0500 | [diff] [blame] | 41 | ; |
Timur Tabi | c5abd7a | 2009-08-20 17:41:11 -0500 | [diff] [blame] | 42 | out_be32(&pic->gcr, MPC85xx_PICGCR_M); |
| 43 | in_be32(&pic->gcr); |
Kumar Gala | 4f6280e | 2008-08-19 14:46:36 -0500 | [diff] [blame] | 44 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 45 | *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; |
Kumar Gala | 4f6280e | 2008-08-19 14:46:36 -0500 | [diff] [blame] | 46 | |
| 47 | /* PIE is same as DIE, dec interrupt enable */ |
Boschung, Rainer | 4728fcf | 2014-06-03 09:05:12 +0200 | [diff] [blame] | 48 | mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE); |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 49 | |
| 50 | #ifdef CONFIG_INTERRUPTS |
Andy Fleming | 9ae360f | 2008-02-27 15:50:50 -0600 | [diff] [blame] | 51 | pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ |
Andrew Klossner | 7ddfafc | 2008-08-21 07:12:26 -0700 | [diff] [blame] | 52 | debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1); |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 53 | |
| 54 | pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ |
Andrew Klossner | 7ddfafc | 2008-08-21 07:12:26 -0700 | [diff] [blame] | 55 | debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2); |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 56 | |
| 57 | pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ |
Andrew Klossner | 7ddfafc | 2008-08-21 07:12:26 -0700 | [diff] [blame] | 58 | debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3); |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 59 | |
| 60 | #ifdef CONFIG_PCI1 |
| 61 | pic->iivpr8 = 0x810008; /* enable pci1 interrupts */ |
Andrew Klossner | 7ddfafc | 2008-08-21 07:12:26 -0700 | [diff] [blame] | 62 | debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8); |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 63 | #endif |
| 64 | #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) |
| 65 | pic->iivpr9 = 0x810009; /* enable pci1 interrupts */ |
Andrew Klossner | 7ddfafc | 2008-08-21 07:12:26 -0700 | [diff] [blame] | 66 | debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9); |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 67 | #endif |
| 68 | #ifdef CONFIG_PCIE1 |
| 69 | pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */ |
Andrew Klossner | 7ddfafc | 2008-08-21 07:12:26 -0700 | [diff] [blame] | 70 | debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10); |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 71 | #endif |
| 72 | #ifdef CONFIG_PCIE3 |
| 73 | pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */ |
Andrew Klossner | 7ddfafc | 2008-08-21 07:12:26 -0700 | [diff] [blame] | 74 | debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11); |
Andy Fleming | f08233c | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 75 | #endif |
| 76 | |
| 77 | pic->ctpr=0; /* 40080 clear current task priority register */ |
| 78 | #endif |
| 79 | |
John Schmoller | a9cecd5 | 2011-03-10 16:09:26 -0600 | [diff] [blame] | 80 | #ifdef CONFIG_POST |
| 81 | post_word_store(post_word); |
| 82 | #endif |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 83 | } |
| 84 | |
Kumar Gala | 4f6280e | 2008-08-19 14:46:36 -0500 | [diff] [blame] | 85 | /* Install and free a interrupt handler. Not implemented yet. */ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 86 | |
| 87 | void |
| 88 | irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) |
| 89 | { |
| 90 | return; |
| 91 | } |
| 92 | |
| 93 | void |
| 94 | irq_free_handler(int vec) |
| 95 | { |
| 96 | return; |
| 97 | } |
| 98 | |
Kumar Gala | 4f6280e | 2008-08-19 14:46:36 -0500 | [diff] [blame] | 99 | void timer_interrupt_cpu(struct pt_regs *regs) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 100 | { |
Kumar Gala | 4f6280e | 2008-08-19 14:46:36 -0500 | [diff] [blame] | 101 | /* PIS is same as DIS, dec interrupt status */ |
wdenk | f3da7cc | 2005-05-13 22:49:36 +0000 | [diff] [blame] | 102 | mtspr(SPRN_TSR, TSR_PIS); |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 103 | } |
| 104 | |
Jon Loeliger | 526e5ce | 2007-07-09 19:06:00 -0500 | [diff] [blame] | 105 | #if defined(CONFIG_CMD_IRQ) |
Kumar Gala | 4f6280e | 2008-08-19 14:46:36 -0500 | [diff] [blame] | 106 | /* irqinfo - print information about PCI devices,not implemented. */ |
Simon Glass | ed38aef | 2020-05-10 11:40:03 -0600 | [diff] [blame] | 107 | int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 108 | { |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 109 | return 0; |
| 110 | } |
Jon Loeliger | 526e5ce | 2007-07-09 19:06:00 -0500 | [diff] [blame] | 111 | #endif |