Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 2 | /* |
Albert ARIBAUD | 340983d | 2011-04-22 19:41:02 +0200 | [diff] [blame] | 3 | * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 4 | * |
| 5 | * Based on original Kirkwood support which is |
| 6 | * (C) Copyright 2009 |
| 7 | * Marvell Semiconductor <www.marvell.com> |
| 8 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 9 | */ |
| 10 | |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 11 | #include <config.h> |
Simon Glass | 8e16b1e | 2019-12-28 10:45:05 -0700 | [diff] [blame] | 12 | #include <init.h> |
Lei Wen | 749941a | 2011-10-24 16:27:32 +0000 | [diff] [blame] | 13 | #include <asm/arch/cpu.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 14 | #include <asm/global_data.h> |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 15 | |
| 16 | DECLARE_GLOBAL_DATA_PTR; |
| 17 | |
| 18 | /* |
| 19 | * orion5x_sdram_bar - reads SDRAM Base Address Register |
| 20 | */ |
| 21 | u32 orion5x_sdram_bar(enum memory_bank bank) |
| 22 | { |
| 23 | struct orion5x_ddr_addr_decode_registers *winregs = |
| 24 | (struct orion5x_ddr_addr_decode_registers *) |
Rogan Dawes | bb6a4e6 | 2011-04-13 23:54:53 +0530 | [diff] [blame] | 25 | ORION5X_DRAM_BASE; |
Albert Aribaud | ac2ba9e | 2010-06-17 19:36:07 +0530 | [diff] [blame] | 26 | |
| 27 | u32 result = 0; |
| 28 | u32 enable = 0x01 & winregs[bank].size; |
| 29 | |
| 30 | if ((!enable) || (bank > BANK3)) |
| 31 | return 0; |
| 32 | |
| 33 | result = winregs[bank].base; |
| 34 | return result; |
| 35 | } |
Heiko Schocher | 0e2412a | 2010-09-17 13:10:42 +0200 | [diff] [blame] | 36 | int dram_init (void) |
| 37 | { |
| 38 | /* dram_init must store complete ramsize in gd->ram_size */ |
| 39 | gd->ram_size = get_ram_size( |
Albert ARIBAUD | a960673 | 2011-07-03 05:55:33 +0000 | [diff] [blame] | 40 | (long *) orion5x_sdram_bar(0), |
Tom Rini | db9c39e | 2022-12-04 10:04:51 -0500 | [diff] [blame] | 41 | CFG_MAX_RAM_BANK_SIZE); |
Heiko Schocher | 0e2412a | 2010-09-17 13:10:42 +0200 | [diff] [blame] | 42 | return 0; |
| 43 | } |
| 44 | |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 45 | int dram_init_banksize(void) |
Heiko Schocher | 0e2412a | 2010-09-17 13:10:42 +0200 | [diff] [blame] | 46 | { |
| 47 | int i; |
| 48 | |
| 49 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
| 50 | gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); |
| 51 | gd->bd->bi_dram[i].size = get_ram_size( |
Albert ARIBAUD | a960673 | 2011-07-03 05:55:33 +0000 | [diff] [blame] | 52 | (long *) (gd->bd->bi_dram[i].start), |
Tom Rini | db9c39e | 2022-12-04 10:04:51 -0500 | [diff] [blame] | 53 | CFG_MAX_RAM_BANK_SIZE); |
Heiko Schocher | 0e2412a | 2010-09-17 13:10:42 +0200 | [diff] [blame] | 54 | } |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 55 | |
| 56 | return 0; |
Heiko Schocher | 0e2412a | 2010-09-17 13:10:42 +0200 | [diff] [blame] | 57 | } |